专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6040632A Multiple sized die 失效
标题翻译：多尺寸模具
公开(公告)号：US6040632A
公开(公告)日：2000-03-21
申请号：US6784
申请日：1998-01-14
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/485 , H01L27/10
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/19043
摘要： A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.
摘要翻译：多尺寸集成电路（IC）管芯和制造多尺寸IC管芯的方法包括在半导体晶片上形成多个IC管芯。每个IC芯片周围都有多排接合焊盘。每个IC管芯的独立行上的相邻接合焊盘电连接在一起，使得连接到任何一个连接的接合焊盘产生相同的结果。多个划线区将晶片上的每个IC芯片分开，划线条限定每个IC芯片之间的宽度。焊盘行位于划痕街区域。可以通过划片晶片来选择性地从IC芯片去除不同行的焊盘，以便包括一行或多行接合焊盘，从而允许一个IC管芯设计具有多个尺寸。只要在周围保持至少两排接合焊盘，则与晶片分离的IC裸片仍可具有更小的尺寸。

2. 发明授权

US5568683A Method of cooling a packaged electronic device 失效
标题翻译：冷却电子装置的方法
公开(公告)号：US5568683A
公开(公告)日：1996-10-29
申请号：US472320
申请日：1995-06-07
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K3/30
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

3. 发明授权

US5463529A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5463529A
公开(公告)日：1995-10-31
申请号：US317968
申请日：1994-10-04
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

4. 发明授权

US5973393A Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits 失效
标题翻译：集成电路可堆叠成型引线框架球栅阵列封装的装置和方法
公开(公告)号：US5973393A
公开(公告)日：1999-10-26
申请号：US771636
申请日：1996-12-20
申请人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
发明人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
IPC分类号： H01L23/29 , H01L23/12 , H01L23/31 , H01L23/50 , H01L25/10 , H01L25/11 , H01L25/18 , H05K3/34 , H01L23/02 , H01L23/28
CPC分类号： H01L23/3107 , H01L25/105 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K3/3436
摘要： An apparatus and method for packaging an integrated circuit having a semiconductor die with electronic circuitry disposed thereon includes lead frames for mounting thereon solder balls of a ball grid array packaging structure. In one embodiment, the semiconductor die is coupled to conductors of the lead frame via gold wires attached to both the semiconductor die and the lead frame. The lead frame is encapsulated in plastic with apertures disposed therein for exposing upper and lower portions of conductors of the lead frame. The apertures are filled with solder balls to contact both the upper and lower portions of the lead frame conductors. Solder balls on the top of one integrated circuit package may be connected to mating solder balls on the bottom of another integrated circuit package, and so on, thereby achieving multiple stacking of integrated circuit packages.
摘要翻译：一种用于封装具有设置在其上的电子电路的半导体管芯的集成电路的装置和方法，包括用于安装在球栅阵列封装结构上的焊球的引线框架。在一个实施例中，半导体管芯经由连接到半导体管芯和引线框架两者的金线耦合到引线框架的导体。引线框架封装在塑料中，其中设置有孔，用于暴露引线框架的导体的上部和下部。孔被填充有焊球以接触引线框架导体的上部和下部。一个集成电路封装顶部的焊球可以连接到另一个集成电路封装的底部上的匹配焊球等，从而实现集成电路封装的多个堆叠。

5. 发明授权

US6114189A Molded array integrated circuit package 失效
标题翻译：成型阵列集成电路封装
公开(公告)号：US6114189A
公开(公告)日：2000-09-05
申请号：US927704
申请日：1997-09-10
申请人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
发明人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
IPC分类号： H01L21/56 , H01L23/31 , H01L21/44
CPC分类号： H01L21/565 , H01L23/3128 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.
摘要翻译：本发明的一个方面涉及一种半导体衬底。在本发明的一个实施例中，半导体衬底包括具有形成在其上的导电迹线的第一和第二表面的封装衬底，以及用于在所选择的导电迹线之间提供电连接的结构，适于提供包装衬底的第一表面上的管芯附着区域与半导体管芯的物理连接，管芯附接区域具有用于在管芯和第一表面上的导电迹线之间提供电连接的导电触点，封装框架，将封装衬底连接到封装框架的至少一个衬底带，衬底带子与封装基板和封装框架整体形成。

6. 发明授权

US5973397A Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density 失效
标题翻译：有利地组合引线键合和制图技术以增加集成电路I / O焊盘密度的半导体器件和制造方法
公开(公告)号：US5973397A
公开(公告)日：1999-10-26
申请号：US955929
申请日：1997-10-22
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/498 , H01L23/04
CPC分类号： H01L24/91 , H01L23/49811 , H01L23/49833 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/14
摘要： A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures. Each conductor has a first end connected to a member of the set of bond traces and an opposed second end connected to a corresponding member of a portion of the set of I/O pads. Each of the remaining members of the I/O pads are connected to respective bond traces adjacent to the die cavity by bonding wires. By combining TAB and wire bonding techniques, the number of I/O pads per unit of upper surface area of the integrated circuit may be increased.
摘要翻译：提出了一种半导体器件和制造方法，其有利地组合TAB和引线键合技术以增加集成电路I / O焊盘密度。半导体器件包括集成电路，衬底和载体膜（即，TAB带）。集成电路具有布置在上表面上的一组输入/输出（I / O）焊盘。衬底在上表面内具有模腔，并且在模腔周围设置一组粘合迹线。集成电路的下表面附着在模腔内的基板上。载体膜位于衬底的上表面上，使得集成电路的上表面通过裸片孔露出，并且该组接合迹线的部件的一部分通过一组接合轨迹孔的相应构件暴露。每个导体具有连接到该组接合迹线的构件的第一端和连接到该组I / O焊盘的一部分的对应构件的相对的第二端。 I / O焊盘的每个剩余部件通过接合线连接到与模腔相邻的各个焊接迹线。通过组合TAB和引线键合技术，可以增加集成电路的每单位上表面积的I / O焊盘的数量。

7. 发明授权

US5353193A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5353193A
公开(公告)日：1994-10-04
申请号：US023981
申请日：1993-02-26
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

8. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

9. 发明授权

US08525312B2 Area array quad flat no-lead (QFN) package 有权
标题翻译：区域阵列四边形无引线（QFN）封装
公开(公告)号：US08525312B2
公开(公告)日：2013-09-03
申请号：US13208822
申请日：2011-08-12
申请人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
发明人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/50 , H01L21/60
CPC分类号： H01L23/49537 , H01L21/4821 , H01L23/3121 , H01L23/49575 , H01L23/49861 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/01322 , H01L2924/01327 , H01L2924/07811 , H01L2924/12042 , H01L2924/1434 , H01L2924/1436 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2224/83
摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
摘要翻译：微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。微电子元件可以具有与引线框架的接合焊盘电连接的触点。

10. 发明申请

US20130037925A1 AREA ARRAY QFN 有权
标题翻译：区域阵列QFN
公开(公告)号：US20130037925A1
公开(公告)日：2013-02-14
申请号：US13208822
申请日：2011-08-12
申请人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
发明人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/50 , H01L21/60
CPC分类号： H01L23/49537 , H01L21/4821 , H01L23/3121 , H01L23/49575 , H01L23/49861 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/01322 , H01L2924/01327 , H01L2924/07811 , H01L2924/12042 , H01L2924/1434 , H01L2924/1436 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2224/83
摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
摘要翻译：微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。微电子元件可以具有与引线框架的接合焊盘电连接的触点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式