专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06255172B1 Electrically erasable non-volatile memory 有权
标题翻译：电可擦除非易失性存储器
公开(公告)号：US06255172B1
公开(公告)日：2001-07-03
申请号：US09567918
申请日：2000-05-10
申请人： Chih-Jen Huang , Auter Wu , Shih-Fang Hong
发明人： Chih-Jen Huang , Auter Wu , Shih-Fang Hong
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method of manufacturing an electrically erasable non-volatile memory is suitable for use on a substrate. The method includes the following steps. First, a tunnel oxide layer is formed on the substrate. A floating gate and a silicon oxide layer/silicon nitride/silicon oxide layer is formed in order on the tunnel oxide layer. Next, a first oxide layer and a silicon nitride spacer are formed in order on the sidewalls of the floating gate. A second oxide layer is formed along the surface of the above entire structure. A third oxide layer is formed on the substrate on both sides of the silicon nitride spacer by oxidation. A patterned conductive layer on the substrate to serve as a control gate and a select transistor gate is formed above the substrate. Using the select transistor gate as a mask, the exposed part of the third oxide layer is removed to make the residual third oxide layer serve as a gate oxide layer of the select transistor. Finally, ion implantation is performed on the substrate to form source and drain regions.
摘要翻译：制造电可擦除非易失性存储器的方法适用于基板。该方法包括以下步骤。首先，在基板上形成隧道氧化层。在隧道氧化物层上依次形成浮置栅极和氧化硅层/氮化硅/氧化硅层。接下来，在浮栅的侧壁上依次形成第一氧化物层和氮化硅间隔物。沿着上述整个结构的表面形成第二氧化物层。通过氧化在氮化硅间隔物的两侧的基板上形成第三氧化物层。在衬底上形成用作控制栅极和选择晶体管栅极的图案化导电层。使用选择晶体管栅极作为掩模，去除第三氧化物层的暴露部分，使剩余的第三氧化物层用作选择晶体管的栅极氧化物层。最后，在衬底上进行离子注入以形成源区和漏区。

2. 发明授权

US06177362B1 Fabrication method for gate structure having gate dielectric layers of different thickness 有权
标题翻译：具有不同厚度的栅极电介质层的栅极结构的制造方法
公开(公告)号：US06177362B1
公开(公告)日：2001-01-23
申请号：US09375877
申请日：1999-08-17
申请人： Chih-Jen Huang , Shih-Fang Hong
发明人： Chih-Jen Huang , Shih-Fang Hong
IPC分类号： H01L21469
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/105 , H01L27/11546
摘要： A method for fabricating a gate structure which has gate dielectric layers of different thicknesses. Since the conducting layer and the protective layer are formed respectively on the dielectric layer after the formation the dielectric layer, the dielectric layer and the photoresist involved in the photolithographic etching are effectively isolated from each other. Also, the dielectric layer is formed by performing oxidation once, so the dielectric layer formed as such has different compositions from that of the dielectric layer formed by double oxidation. Thus, the contamination of the dielectric layer by the photoresist is greatly reduced while the quality and reliability of the dielectric layer are greatly improved.
摘要翻译：一种制造具有不同厚度的栅极电介质层的栅极结构的方法。由于导电层和保护层在形成之后分别形成在电介质层上，所以电介质层，介电层和涉及光刻蚀刻的光致抗蚀剂彼此有效隔离。此外，通过进行氧化一次形成电介质层，因此形成的电介质层与通过双重氧化形成的电介质层的组成不同。因此，通过光致抗蚀剂对电介质层的污染大大降低，同时电介质层的质量和可靠性大大提高。

3. 发明授权

US06228718B1 Method of fabricating a self-aligned split gate of a flash memory 失效
标题翻译：制造闪存的自对准分裂门的方法
公开(公告)号：US06228718B1
公开(公告)日：2001-05-08
申请号：US09468558
申请日：1999-12-21
申请人： Chih-Jen Huang , Shih-Fang Hong
发明人： Chih-Jen Huang , Shih-Fang Hong
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： The present invention is a method of fabricating a self-aligned split gate of flash memory. Aligned layers are formed on predetermined source regions and predetermined drain regions in advance. Spacers are formed on the sidewalls of the aligned layers. An etching rate of the spacers is different from an etching rate of the aligned layers. Therefore, if misalignment occurs during the patterning process to form a split control gate layer, the spacers also can be left after the aligned layer is removed. The remaining spacers serves as a implant mask during the implantion for the sources and the drains formation, so that the sources and the drains are formed in the respective positions of the aligned layers by self-alignment.
摘要翻译：本发明是制造闪存的自对准分裂门的方法。对准层预先在预定的源极区域和预定的漏极区域上形成。间隔物形成在对准层的侧壁上。间隔物的蚀刻速率与对准层的蚀刻速率不同。因此，如果在形成分割控制栅极层的图案化工艺期间发生不对准，则在去除对准层之后也可以留下间隔物。剩余的间隔物在用于源和漏极形成的植入期间用作植入物掩模，使得源和漏极通过自对准形成在对准层的相应位置。

4. 发明申请

US20090224327A1 PLANE MOS AND THE METHOD FOR MAKING THE SAME 审中-公开
标题翻译：平面MOS及其制作方法
公开(公告)号：US20090224327A1
公开(公告)日：2009-09-10
申请号：US12041666
申请日：2008-03-04
申请人： En-Chiuan Liou , Shih-Fang Hong , Chih-Wei Yang , Yu-Hsin Lin , Rai-Min Huang
发明人： En-Chiuan Liou , Shih-Fang Hong , Chih-Wei Yang , Yu-Hsin Lin , Rai-Min Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L27/1211 , H01L29/785
摘要： A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.
摘要翻译：平面MOS包括基板，其表面基本上平行于设置在基板上的基板的表面的绝缘体层，直接设置在绝缘体层上的栅极，源极和漏极以及设置在源极和源极之间的栅极沟道排水并与门接触。

5. 发明授权

US08569127B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569127B2
公开(公告)日：2013-10-29
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L21/8238 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

6. 发明申请

US20130241001A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241001A1
公开(公告)日：2013-09-19
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式