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1. 发明授权

US08569127B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569127B2
公开(公告)日：2013-10-29
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L21/8238 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

2. 发明申请

US20130241001A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130241001A1
公开(公告)日：2013-09-19
申请号：US13418835
申请日：2012-03-13
申请人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
发明人： Chien-Yang Chen , Chen-Hua Tsai , Shih-Fang Hong , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L27/088 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/28518 , H01L21/76814 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
摘要翻译：对半导体装置的制造方法进行说明。提供了其上具有多晶硅电阻器的基板。在覆盖多晶硅电阻器的衬底上形成介电层。蚀刻电介质层以在多晶硅电阻器上形成接触开口，其过蚀刻到多晶硅电阻器中。在接触开口中的多晶硅电阻器上形成金属硅化物层。金属材料填充在接触开口中。去除介电层，金属材料和多晶硅电阻的一部分的一部分以露出金属硅化物层。在金属硅化物层上形成金属接触。

3. 发明授权

US08860181B2 Thin film resistor structure 有权
标题翻译：薄膜电阻器结构
公开(公告)号：US08860181B2
公开(公告)日：2014-10-14
申请号：US13413669
申请日：2012-03-07
申请人： Ming-Te Wei , Po-Chao Tsao , Chen-Hua Tsai , Chien-Yang Chen , Chia-Jui Liang , Ming-Tsung Chen
发明人： Ming-Te Wei , Po-Chao Tsao , Chen-Hua Tsai , Chien-Yang Chen , Chia-Jui Liang , Ming-Tsung Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.
摘要翻译：薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在底部ILD和顶部ILD。

4. 发明申请

US20130234292A1 THIN FILM RESISTOR STRUCTURE 有权
标题翻译：薄膜电阻结构
公开(公告)号：US20130234292A1
公开(公告)日：2013-09-12
申请号：US13413669
申请日：2012-03-07
申请人： Ming-Te Wei , Po-Chao Tsao , Chen-Hua Tsai , Chien-Yang Chen , Chia-Jui Liang , Ming-Tsung Chen
发明人： Ming-Te Wei , Po-Chao Tsao , Chen-Hua Tsai , Chien-Yang Chen , Chia-Jui Liang , Ming-Tsung Chen
IPC分类号： H01L29/02
CPC分类号： H01L23/5228 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.
摘要翻译：薄膜电阻器结构包括基板，设置在基板上的平坦底部ILD（层间电介质），设置在底部ILD中的多个第一触点，并且第一触点的每个顶表面与顶部底部ILD的表面; 设置在底部ILD上的平顶部ILD，设置在顶部ILD中的多个第二触点，并且第二触点的每个顶部表面位于与顶部ILD的顶表面相同的水平面上，并且薄膜电阻器设置在底部ILD和顶部ILD。

5. 发明授权

US08546962B2 Mark structure and method for measuring alignment accuracy between former layer and latter layer 有权
标题翻译：用于测量前层和后层之间的对准精度的标记结构和方法
公开(公告)号：US08546962B2
公开(公告)日：2013-10-01
申请号：US13042721
申请日：2011-03-08
申请人： Jun-Chi Huang , Po-Chao Tsao , Ming-Te Wei
发明人： Jun-Chi Huang , Po-Chao Tsao , Ming-Te Wei
IPC分类号： H01L23/544 , G01B15/00 , H01J37/00 , G01N23/225
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.
摘要翻译：描述了用电子束检查（EBI）测量前一层和后一层之间的对准精度的标记结构。标记结构包括多个分割，每个分割部分包括至少一个区域，该区域包括多个部分，每个部分设置有前一层的一对图案和后一层的图案。在每个区域中，所有部分在前一层的图案和后一层的图案之间的方向上具有相同的距离。方向上的距离在标记结构的分割区域之间变化。

6. 发明申请

US20120012904A1 METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：金属氧化物半导体晶体管及其制造方法
公开(公告)号：US20120012904A1
公开(公告)日：2012-01-19
申请号：US12837475
申请日：2010-07-15
申请人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
发明人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66689 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/7816 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
摘要翻译：公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

7. 发明授权

US08816409B2 Metal-oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US08816409B2
公开(公告)日：2014-08-26
申请号：US12837475
申请日：2010-07-15
申请人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
发明人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
IPC分类号： H01L21/00 , H01L29/165 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66689 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/7816 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
摘要翻译：公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

8. 发明授权

US08575034B2 Fabricating method of semiconductor element 有权
标题翻译：半导体元件的制造方法
公开(公告)号：US08575034B2
公开(公告)日：2013-11-05
申请号：US13283690
申请日：2011-10-28
申请人： Ming-Te Wei , Po-Chao Tsao , Ming-Tsung Chen
发明人： Ming-Te Wei , Po-Chao Tsao , Ming-Tsung Chen
IPC分类号： H01L21/461
CPC分类号： H01L21/28 , H01L21/823437 , H01L27/0207
摘要： The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.
摘要翻译：半导体元件的制造方法技术领域本发明涉及半导体元件的制造方法。首先，提供基板，并且在基板上形成具有第一宽度的第一布局结构。然后，形成蚀刻掩模以覆盖第一布局结构，并且蚀刻掩模暴露第一布局结构的一部分。之后，用蚀刻掩模蚀刻第一布局结构以形成具有第二宽度的第二布局结构。第二宽度小于第一宽度。该制造方法能够完成两个不同方向的栅极结构的制造。因此，布局灵活性得到改善。

9. 发明授权

US09136348B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09136348B2
公开(公告)日：2015-09-15
申请号：US13417337
申请日：2012-03-12
申请人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
发明人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66492 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.
摘要翻译：半导体结构包括设置在基板上并具有外部间隔件的栅极结构，设置在基板中并与栅极结构相邻的凹槽，填充凹部的掺杂的外延材料，包括未掺杂的外延材料的盖层，所述掺杂的外延材料是设置在所述覆盖层下方并且夹在所述掺杂的外延材料和所述覆盖层之间的轻掺杂漏极，以及设置在所述覆盖层上并覆盖所述掺杂外延材料以与所述外部间隔物一起覆盖所述覆盖层的硅化物而不直接接触轻掺杂的漏极。

10. 发明申请

US20130234261A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
公开(公告)号：US20130234261A1
公开(公告)日：2013-09-12
申请号：US13417337
申请日：2012-03-12
申请人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
发明人： Ming-Te Wei , Shin-Chuan Huang , Yu-Hsiang Hung , Po-Chao Tsao , Chia-Jui Liang , Ming-Tsung Chen , Chia-Wen Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66492 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

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