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1. 发明申请

US20090224327A1 PLANE MOS AND THE METHOD FOR MAKING THE SAME 审中-公开
标题翻译：平面MOS及其制作方法
公开(公告)号：US20090224327A1
公开(公告)日：2009-09-10
申请号：US12041666
申请日：2008-03-04
申请人： En-Chiuan Liou , Shih-Fang Hong , Chih-Wei Yang , Yu-Hsin Lin , Rai-Min Huang
发明人： En-Chiuan Liou , Shih-Fang Hong , Chih-Wei Yang , Yu-Hsin Lin , Rai-Min Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L27/1211 , H01L29/785
摘要： A plane MOS includes a substrate, an insulator layer whose surface is substantially parallel with the surface of the substrate disposed on the substrate, a gate, a source and a drain directly disposed on the insulator layer and a gate channel disposed between the source and the drain and contacting the gate.
摘要翻译：平面MOS包括基板，其表面基本上平行于设置在基板上的基板的表面的绝缘体层，直接设置在绝缘体层上的栅极，源极和漏极以及设置在源极和源极之间的栅极沟道排水并与门接触。

2. 发明申请

US20090250754A1 PARTIALLY DEPLETED SILICON-ON-INSULATOR METAL OXIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：部分绝缘硅绝缘体金属氧化物半导体器件
公开(公告)号：US20090250754A1
公开(公告)日：2009-10-08
申请号：US12061168
申请日：2008-04-02
申请人： Yu-Hsin Lin , Rai-Min Huang , En-Chiuan Liou , Chih-Wei Yang
发明人： Yu-Hsin Lin , Rai-Min Huang , En-Chiuan Liou , Chih-Wei Yang
IPC分类号： H01L27/12 , H01L21/00
CPC分类号： H01L29/78654 , H01L29/66772 , H01L29/7843 , H01L29/78612
摘要： A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate.
摘要翻译：提供了部分耗尽的绝缘体上的金属氧化物半导体（PD-SOI MOS）器件。 PD-SOI MOS器件包括在绝缘体上硅衬底上的栅极结构，栅极结构旁边的绝缘体上硅衬底中的源极和漏极区域以及源极区域和/或栅极结构的界面中的硅错位泄漏路径绝缘体上硅衬底。

3. 发明申请

US20130045576A1 METHOD FOR FABRICATING FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE 有权
标题翻译：用于制造具有精细结构的场效应晶体管的方法
公开(公告)号：US20130045576A1
公开(公告)日：2013-02-21
申请号：US13213092
申请日：2011-08-19
申请人： Shih-Hung Tsai , Rai-Min Huang , Chien-Ting Lin
发明人： Shih-Hung Tsai , Rai-Min Huang , Chien-Ting Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7854
摘要： A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.
摘要翻译：制造具有鳍结构的场效应晶体管的方法包括以下顺序。首先，提供基板，并且在基板上形成至少一个翅片结构。然后，执行蚀刻处理以使鳍结构中的至少一个上边缘圆弧。最后，形成覆盖翅片结构的门。

4. 发明申请

US20120299099A1 FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US20120299099A1
公开(公告)日：2012-11-29
申请号：US13116018
申请日：2011-05-26
申请人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/786 , H01L21/3205
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

5. 发明授权

US08853013B2 Method for fabricating field effect transistor with fin structure 有权
标题翻译：具有翅片结构的场效应晶体管的制造方法
公开(公告)号：US08853013B2
公开(公告)日：2014-10-07
申请号：US13213092
申请日：2011-08-19
申请人： Shih-Hung Tsai , Rai-Min Huang , Chien-Ting Lin
发明人： Shih-Hung Tsai , Rai-Min Huang , Chien-Ting Lin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7854
摘要： A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.
摘要翻译：制造具有鳍结构的场效应晶体管的方法包括以下顺序。首先，提供基板，并且在基板上形成至少一个翅片结构。然后，执行蚀刻处理以使鳍结构中的至少一个上边缘圆弧。最后，形成覆盖翅片结构的门。

6. 发明授权

US08772860B2 FINFET transistor structure and method for making the same 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US08772860B2
公开(公告)日：2014-07-08
申请号：US13116018
申请日：2011-05-26
申请人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

7. 发明申请

US20130280900A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
标题翻译：具有金属栅的半导体器件的制造方法
公开(公告)号：US20130280900A1
公开(公告)日：2013-10-24
申请号：US13454337
申请日：2012-04-24
申请人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
发明人： Chien-Ming Lai , Rai-Min Huang , Tong-Jyun Huang , Che-Hua Hsu , Yi-Wen Chen
IPC分类号： H01L21/283
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
摘要翻译：提供一种具有金属栅极的半导体器件的制造方法。第一和第二栅极沟槽分别形成在第一和第二半导体器件中。工作功能金属层形成在第一和第二栅极沟槽中。在基板上形成屏蔽层。执行第一去除步骤，使得剩余的屏蔽层位于第二栅极沟槽的底部并填充第一栅极沟槽。执行第二去除步骤，使得剩余的屏蔽层位于第一栅极沟槽的底部，以在第一栅极沟槽的侧壁和第二栅极沟槽中露出功函数金属层。除去未被剩余屏蔽层覆盖的功函数金属层，使剩余的功函数金属层仅在第一栅极沟槽的底部。剩下的屏蔽层被去除。

8. 发明申请

US20130052781A1 Method of Forming Non-planar FET 有权
标题翻译：形成非平面FET的方法
公开(公告)号：US20130052781A1
公开(公告)日：2013-02-28
申请号：US13218438
申请日：2011-08-25
申请人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
发明人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
IPC分类号： H01L21/8232
CPC分类号： H01L29/7851 , H01L21/845 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
摘要翻译：提供一种形成非平面FET的方法。提供基板。在衬底上限定有源区和周边区。在基板的有源区域中形成多个VSTI。去除每个VSTI的一部分以露出衬底的侧壁的一部分。然后，在衬底上形成导体层，然后将其图案化以在周边区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。最后，源极/漏极区域形成在非平面FET栅极的两侧。

9. 发明授权

US08691651B2 Method of forming non-planar FET 有权
标题翻译：形成非平面FET的方法
公开(公告)号：US08691651B2
公开(公告)日：2014-04-08
申请号：US13218438
申请日：2011-08-25
申请人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
发明人： Sheng-Huei Dai , Rai-Min Huang , Chen-Hua Tsai , Shih-Hung Tsai , Chien-Ting Lin
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/845 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
摘要翻译：提供一种形成非平面FET的方法。提供基板。在衬底上限定有源区和周边区。在基板的有源区域中形成多个VSTI。去除每个VSTI的一部分以露出衬底的侧壁的一部分。然后，在衬底上形成导体层，然后将其图案化以在外围区域中形成平面FET栅极，并且在有源区域中同时形成非平面FET栅极。最后，源极/漏极区域形成在非平面FET栅极的两侧。

10. 发明授权

US09105660B2 Fin-FET and method of forming the same 有权
标题翻译： Fin-FET及其形成方法
公开(公告)号：US09105660B2
公开(公告)日：2015-08-11
申请号：US13211334
申请日：2011-08-17
申请人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
发明人： Chen-Hua Tsai , Rai-Min Huang , Sheng-Huei Dai , Chun-Hsien Lin
IPC分类号： H01L29/66 , H01L21/02 , H01L21/20 , H01L29/78
CPC分类号： H01L29/7853 , H01L21/02647 , H01L21/2022 , H01L29/1054 , H01L29/16 , H01L29/66795 , H01L29/7842 , H01L29/785 , H01L2029/7858
摘要： A method of forming a Fin-FET is provided. A substrate is provided, then a mask layer is formed thereabove. A first trench is formed in the substrate and the mask layer. A semiconductor layer is formed in the first trench. Next, the mask layer is removed such that the semi-conductive layer becomes a fin structure embedded in the substrate and protruded above the substrate. Finally, a gate layer is formed on the fin structure.
摘要翻译：提供了形成Fin-FET的方法。提供衬底，然后在其上形成掩模层。在衬底和掩模层中形成第一沟槽。在第一沟槽中形成半导体层。接下来，去除掩模层，使得半导体层变成嵌入在衬底中并突出在衬底上的散热片结构。最后，在鳍结构上形成栅极层。

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