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    • 8. 发明授权
    • Method and apparatus for enabling fast clock phase locking in a phase-locked loop
    • 用于在锁相环中实现快速时钟相位锁定的方法和装置
    • US07263154B2
    • 2007-08-28
    • US10680636
    • 2003-10-07
    • Tse-Hsiang HsuDing-Jen LiuJong-Woei ChenChih-Cheng Chen
    • Tse-Hsiang HsuDing-Jen LiuJong-Woei ChenChih-Cheng Chen
    • H03D1/24H03L7/06
    • G11B20/10009G11B27/3027G11B2220/216G11B2220/2575H03L7/081H03L7/10
    • In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.
    • 在用于在锁相环中实现快速时钟相位锁定的方法和装置中,采样时钟发生器响应于锁相环的振荡器输出产生采样时钟信号。 检测器单元在采样时钟信号的时钟边沿将输入数字信号采样到锁相环,以获得输入数字信号的多个采样点,并且比较每个时间上相邻的采样点对的逻辑电平,以检测 输入数字信号中的逻辑电平转换。 选择器单元由检测器单元控制,以选择一个采样时钟信号,其中一个采样时钟信号的时钟边沿之一限定了被检测为在输入数字信号中出现逻辑电平转换的间隔,随后 提供给锁相环作为输入锁相时钟信号。
    • 9. 发明申请
    • TRACK AND HOLD CIRCUIT AND RELATED RECEIVING DEVICE WITH TRACK AND HOLD CIRCUIT EMPLOYED THEREIN
    • 跟踪和保持电路跟踪和相关接收设备跟踪并保持已使用的电路
    • US20110181334A1
    • 2011-07-28
    • US12695164
    • 2010-01-28
    • Hung-Chieh TsaiYu-Hsin LinChi-Lun LoJong-Woei Chen
    • Hung-Chieh TsaiYu-Hsin LinChi-Lun LoJong-Woei Chen
    • H03L5/00
    • H03G3/3052H03G1/0088
    • An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
    • 运算电路包括:增益控制电路,被配置为根据一组控制信号在输入信号上提供增益值,其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器,耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器,其中当所述运算电路运行时,所述第一电容器的第一端始终耦合到 运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。