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1. 发明授权

US07263154B2 Method and apparatus for enabling fast clock phase locking in a phase-locked loop 有权
标题翻译：用于在锁相环中实现快速时钟相位锁定的方法和装置
公开(公告)号：US07263154B2
公开(公告)日：2007-08-28
申请号：US10680636
申请日：2003-10-07
申请人： Tse-Hsiang Hsu , Ding-Jen Liu , Jong-Woei Chen , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Ding-Jen Liu , Jong-Woei Chen , Chih-Cheng Chen
IPC分类号： H03D1/24 , H03L7/06
CPC分类号： G11B20/10009 , G11B27/3027 , G11B2220/216 , G11B2220/2575 , H03L7/081 , H03L7/10
摘要： In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.
摘要翻译：在用于在锁相环中实现快速时钟相位锁定的方法和装置中，采样时钟发生器响应于锁相环的振荡器输出产生采样时钟信号。检测器单元在采样时钟信号的时钟边沿将输入数字信号采样到锁相环，以获得输入数字信号的多个采样点，并且比较每个时间上相邻的采样点对的逻辑电平，以检测输入数字信号中的逻辑电平转换。选择器单元由检测器单元控制，以选择一个采样时钟信号，其中一个采样时钟信号的时钟边沿之一限定了被检测为在输入数字信号中出现逻辑电平转换的间隔，随后提供给锁相环作为输入锁相时钟信号。

2. 发明授权

US07075348B2 Differential charge pump with common-mode feedback compensation 有权
标题翻译：差分电荷泵，具有共模反馈补偿
公开(公告)号：US07075348B2
公开(公告)日：2006-07-11
申请号：US10270597
申请日：2002-10-16
申请人： Tse-Hsiang Hsu , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Chih-Cheng Chen
IPC分类号： H03L7/093 , H03F3/45
CPC分类号： H03L7/0896
摘要： A differential charge pump includes a first current, a second current, a first switching device, a second switching device, a first phase inverting switching device, a second phase inverting switching device, and a common mode feedback device. The common mode feedback device is used to adjust the current level exported by the first current source, according to the common mode voltage of the differential charge pump, so that the respective currents exported by the first current source and the second current source are to be the same. The present invention has used the property that the common mode voltage of the differential charge pump should be a constant value, so as to correct the level of the current source. As a result, the current exported by the differential charge pump can be precisely corrected. Also, the present invention only needs one charge pump, so that the structure is simple and the fabrication is easy. In addition, no matter whether there is a rising or falling signal, the correction can be performed. Therefore, it has no issue of shift for the common mode voltage.
摘要翻译：差分电荷泵包括第一电流，第二电流，第一开关装置，第二开关装置，第一相位反相开关装置，第二相位反相开关装置和共模反馈装置。共模反馈装置用于根据差分电荷泵的共模电压来调节由第一电流源输出的电流电平，使得由第一电流源和第二电流源输出的相应电流为一样。本发明使用了差分电荷泵的共模电压应当是一个恒定值，从而校正电流源的电平。结果，可以精确地校正由差动电荷泵输出的电流。此外，本发明仅需要一个电荷泵，使结构简单，制造容易。另外，无论是上升还是下降信号，都可以进行校正。因此，对共模电压没有偏移的问题。

3. 发明授权

US07054250B2 Method and device for jitter enhancement in an optical disc system 有权
标题翻译：用于光盘系统抖动增强的方法和装置
公开(公告)号：US07054250B2
公开(公告)日：2006-05-30
申请号：US10358529
申请日：2003-02-05
申请人： Tse-Hsiang Hsu , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Chih-Cheng Chen
IPC分类号： G11B7/00
CPC分类号： G11B7/0053 , G11B20/24
摘要： A method and device are provided for jitter enhancement in an optical disc system. The optical disc system generates a signal that includes an effective component having a first slew rate, and a pre-pit component having a second slew rate larger than the first slew rate. The signal is fed to a slew rate control module having a predetermined slew rate that is larger than the first slew rate and smaller than the second slew rate. The slew rate control module outputs a component of the signal having a slew rate not larger than the predetermined slew rate, and suppresses a component of the information signal having a slew rate larger than the predetermined slew rate.
摘要翻译：提供了一种用于光盘系统中的抖动增强的方法和装置。光盘系统产生包括具有第一压摆率的有效部件和具有大于第一压摆率的第二转换速率的预凹陷部件的信号。信号被馈送到具有大于第一转换速率并小于第二转换速率的预定转换速率的转换速率控制模块。转换速率控制模块输出具有不大于预定转换速率的转换速率的信号的分量，并且抑制具有大于预定转换速率的转换速率的信息信号的分量。

4. 发明申请

US20090046555A1 WRITE SIGNAL GENERATOR WITH DELAY CALIBRATION 审中-公开
标题翻译：带延迟校准的写信号发生器
公开(公告)号：US20090046555A1
公开(公告)日：2009-02-19
申请号：US12257833
申请日：2008-10-24
申请人： Tse-Hsiang HSU , Chih-Cheng Chen
发明人： Tse-Hsiang HSU , Chih-Cheng Chen
IPC分类号： G11B20/18
CPC分类号： G11B20/10212 , G11B7/00456 , G11B2020/1287 , G11B2020/1461
摘要： An aligned write signal generator with alignment calibration utilizes an alignment unit to align a plurality of write signal. The aligned write signal generator includes a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule, an alignment unit for receiving the plurality of write signals, aligning the write signals and outputting phase adjusted write signals, and a phase calibration unit for receiving the phase adjusted write signals, detecting phase error between the phase adjusted write signals, and outputting phase control signals. The alignment unit further receives the phase control signals to adjust the delay time of each write signal.
摘要翻译：具有对准校准的对准的写入信号发生器利用对准单元对准多个写入信号。对准的写信号发生器包括写信号发生器，用于接收EFM信号，并根据写策略波形产生规则将EFM信号转换为多个写信号;对准单元，用于接收多个写信号，对准写信号并输出相位调整的写入信号，以及相位校准单元，用于接收相位调整的写入信号，检测相位调整的写入信号之间的相位误差，并输出相位控制信号。对准单元还接收相位控制信号以调整每个写入信号的延迟时间。

5. 发明授权

US07457213B2 Write signal generator with delay calibration 失效
标题翻译：具有延迟校准的写信号发生器
公开(公告)号：US07457213B2
公开(公告)日：2008-11-25
申请号：US10868952
申请日：2004-06-17
申请人： Tse-Hsiang Hsu , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Chih-Cheng Chen
IPC分类号： G11B15/52
CPC分类号： G11B20/10212 , G11B7/00456 , G11B2020/1287 , G11B2020/1461
摘要： An aligned write signal generator with alignment calibration utilizes an alignment unit to align a plurality of write signal. The aligned write signal generator includes a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule, an alignment unit for receiving the plurality of write signals, aligning the write signals and outputting phase adjusted write signals, and a phase calibration unit for receiving the phase adjusted write signals, detecting phase error between the phase adjusted write signals, and outputting phase control signals. The alignment unit further receives the phase control signals to adjust the delay time of each write signal.
摘要翻译：具有对准校准的对准的写入信号发生器利用对准单元对准多个写入信号。对准的写信号发生器包括写信号发生器，用于接收EFM信号，并根据写策略波形产生规则将EFM信号转换为多个写信号;对准单元，用于接收多个写信号，对准写信号并输出相位调整的写入信号，以及相位校准单元，用于接收相位调整的写入信号，检测相位调整的写入信号之间的相位误差，并输出相位控制信号。对准单元还接收相位控制信号以调整每个写入信号的延迟时间。

6. 发明授权

US07126384B2 Peak detection circuit with double peak detection stages 有权
标题翻译：具有双峰检测级的峰值检测电路
公开(公告)号：US07126384B2
公开(公告)日：2006-10-24
申请号：US10737746
申请日：2003-12-18
申请人： Tse-Hsiang Hsu , Yung-Yu Lin , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Yung-Yu Lin , Chih-Cheng Chen
IPC分类号： H03K5/153
CPC分类号： G01R19/04
摘要： A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.
摘要翻译：具有双峰检测级的峰值检测电路包括模拟峰值检测器，模数转换器（ADC）和数字峰值检测器。模拟峰值检测器接收模拟输入信号，以第一周期检测模拟输入信号的峰值，并输出模拟峰值信号。 ADC接收模拟峰值信号并将其转换为数字信号。数字峰值检测器接收数字信号，以比第一周期长的第二周期检测数字信号的峰值，并输出数字峰值信号。因此，模拟峰值信号由于泄漏而不会严重衰减，数字峰值信号可以长时间保持数字峰值。

7. 发明授权

US06897691B2 Phase locked loop with low steady state phase errors and calibration circuit for the same 有权
标题翻译：具有低稳态相位误差的锁相环和相同的校准电路
公开(公告)号：US06897691B2
公开(公告)日：2005-05-24
申请号：US10437906
申请日：2003-05-15
申请人： Chih-Cheng Chen , Tse-Hsiang Hsu
发明人： Chih-Cheng Chen , Tse-Hsiang Hsu
IPC分类号： H03L7/081 , H03L7/089 , H03L7/18 , H03L7/00
CPC分类号： H03L7/0891 , H03L7/081 , H03L7/18
摘要： A phase locked loop (PLL) with low steady state phase errors utilizes a delay unit to delay an input signal or a reference clock so as to lower the steady state phase errors of the PLL. A calibration circuit is used to adjust the delay time of the delay unit and includes a signal generator for generating a simulation input signal and a simulation reference clock according to a phase locked clock; a delay unit for delaying the simulation reference clock and generating a delayed reference clock; a phase detector for detecting the phase error between the simulation input signal and the delayed reference clock and generating charge control signals; a charge pump and an integrator for generating an error voltage according to the charge control signals; a delay time control unit for adjusting the delay time of the delay unit according to the error voltage; and a voltage control oscillator for generating the oscillation clock according to a reference control voltage.
摘要翻译：具有低稳态相位误差的锁相环（PLL）利用延迟单元来延迟输入信号或参考时钟，以降低PLL的稳态相位误差。校准电路用于调整延迟单元的延迟时间，并包括用于根据锁相时钟产生模拟输入信号和模拟参考时钟的信号发生器; 延迟单元，用于延迟模拟参考时钟并产生延迟的参考时钟; 相位检测器，用于检测模拟输入信号和延迟的参考时钟之间的相位误差，并产生电荷控制信号; 电荷泵和用于根据充电控制信号产生误差电压的积分器; 延迟时间控制单元，用于根据误差电压调整延迟单元的延迟时间; 以及用于根据参考控制电压产生振荡时钟的电压控制振荡器。

8. 发明授权

US06850102B2 Apparatus for calibrating a charge pump and method therefor 失效
标题翻译：用于校准电荷泵的装置及其方法
公开(公告)号：US06850102B2
公开(公告)日：2005-02-01
申请号：US10253650
申请日：2002-09-25
申请人： Tse-Hsiang Hsu , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Chih-Cheng Chen
IPC分类号： H03L7/089 , H03L7/18 , H03L7/06
CPC分类号： H03L7/0895 , H03L7/18
摘要： A signal calibration apparatus of a charge pump minimizes a current from the charge pump. The signal calibration apparatus includes a detecting circuit, a current adjusting circuit, and a calibrating circuit, wherein the detecting circuit is coupled to the charge pump for outputting a detecting signal according to the direction and magnitude of the current, the current adjusting circuit is coupled to the detecting circuit for outputting a calibrating signal according to the polarity and magnitude of the slew rate for the detection signal; and the calibrating circuit, which consists of a first calibration current source and a second calibration current source, is respectively coupled to the charge pump and the current adjusting circuit for adjusting the first current and the second current by outputting a first calibrating current and second calibrating current to the charge pump.
摘要翻译：电荷泵的信号校准装置使来自电荷泵的电流最小化。信号校准装置包括检测电路，电流调节电路和校准电路，其中检测电路耦合到电荷泵，用于根据电流的方向和幅度输出检测信号，电流调节电路耦合检测电路，用于根据检测信号的转换速率的极性和大小输出校准信号; 并且由第一校准电流源和第二校准电流源组成的校准电路分别耦合到电荷泵和电流调节电路，用于通过输出第一校准电流和第二校准电流来调节第一电流和第二电流电流到电荷泵。

9. 发明授权

US06998891B2 Apparatus for calibrating a charge pump and method therefor 有权
标题翻译：用于校准电荷泵的装置及其方法
公开(公告)号：US06998891B2
公开(公告)日：2006-02-14
申请号：US11010420
申请日：2004-12-14
申请人： Tse-Hsiang Hsu , Chih-Cheng Chen
发明人： Tse-Hsiang Hsu , Chih-Cheng Chen
IPC分类号： H03L7/06
CPC分类号： H03L7/0895 , H03L7/18
摘要： A signal calibration apparatus of a charge pump minimizes a current from the charge pump. The signal calibration apparatus includes a detecting circuit, a current adjusting circuit, and a calibrating circuit, wherein the detecting circuit is coupled to the charge pump for outputting a detecting signal according to the direction and magnitude of the current, the current adjusting circuit is coupled to the detecting circuit for outputting a calibrating signal according to the polarity and magnitude of the slew rate of the detecting signal; and the calibrating circuit, which consists of a first calibration current source and a second calibration current source, is respectively coupled to the charge pump and the current adjusting circuit for adjusting the first current and the second current by outputting a first calibrating current and second calibrating current to the charge pump.
摘要翻译：电荷泵的信号校准装置使来自电荷泵的电流最小化。信号校准装置包括检测电路，电流调节电路和校准电路，其中检测电路耦合到电荷泵，用于根据电流的方向和幅度输出检测信号，电流调节电路耦合检测电路，用于根据检测信号的转换速率的极性和大小输出校准信号; 并且由第一校准电流源和第二校准电流源组成的校准电路分别耦合到电荷泵和电流调节电路，用于通过输出第一校准电流和第二校准电流来调节第一电流和第二电流电流到电荷泵。

10. 发明申请

US20050122875A1 Apparatus and method for optical disk drive signal processing 审中-公开
标题翻译：用于光盘驱动器信号处理的装置和方法
公开(公告)号：US20050122875A1
公开(公告)日：2005-06-09
申请号：US11000945
申请日：2004-12-02
申请人： Chia-Hua Chou , Chih-Cheng Chen , Tse-Hsiang Hsu
发明人： Chia-Hua Chou , Chih-Cheng Chen , Tse-Hsiang Hsu
IPC分类号： G11B5/09 , G11B7/005 , G11B7/007 , G11B20/00 , G11B20/10
CPC分类号： G11B20/10 , G11B7/0053 , G11B7/00736 , G11B7/00745 , G11B7/24082
摘要： The present invention describes an apparatus and method for optical disk drive signal processing. For improving the bandwidth for signal transmitting between an optical disk drive (ODD) controller and an optical pick-up unit (OPU) via a flexible cable, a physical address pre-processing unit is mounted on the optical pick-up unit of a Optical disk drive. The long settling time problem conventionally due to a voltage change in the writing process can be resolved. The apparatus and method extract the physical address in the high-writing process of the Optical disk drive.
摘要翻译：本发明描述了一种用于光盘驱动信号处理的装置和方法。为了通过柔性电缆提高光盘驱动器（ODD）控制器和光拾取单元（OPU）之间信号传输的带宽，物理地址预处理单元安装在光学拾取单元磁盘驱动器。可以解决通常由于写入处理中的电压变化导致的长的建立时间问题。该设备和方法在光盘驱动器的高写入过程中提取物理地址。

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