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1. 发明申请

US20120274411A1 Pulse Width Modulation Driving IC and Pulse Width Modulation Output Signal Generating Method 有权
标题翻译：脉宽调制驱动IC和脉宽调制输出信号产生方法
公开(公告)号：US20120274411A1
公开(公告)日：2012-11-01
申请号：US13172816
申请日：2011-06-29
申请人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
发明人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.
摘要翻译：本发明公开了一种脉宽调制驱动IC。脉宽调制驱动IC包括用于接收第一信号的第一引脚，用于接收第二信号的第二引脚，用于将第一信号与参考电压进行比较的比较单元，以产生指示操作模式的比较结果以及输出单元，用于根据第一信号，第二信号和比较结果输出脉宽调制输出信号。

2. 发明授权

US08519802B2 Pulse width modulation driving IC and pulse width modulation output signal generating method 有权
标题翻译：脉宽调制驱动IC和脉宽调制输出信号产生方法
公开(公告)号：US08519802B2
公开(公告)日：2013-08-27
申请号：US13172816
申请日：2011-06-29
申请人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
发明人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.
摘要翻译：本发明公开了一种脉宽调制驱动IC。脉宽调制驱动IC包括用于接收第一信号的第一引脚，用于接收第二信号的第二引脚，用于将第一信号与参考电压进行比较的比较单元，以产生指示操作模式的比较结果以及输出单元，用于根据第一信号，第二信号和比较结果输出脉宽调制输出信号。

3. 发明授权

US08362588B2 Semiconductor chip with coil element over passivation layer 有权
公开(公告)号：US08362588B2
公开(公告)日：2013-01-29
申请号：US13159147
申请日：2011-06-13
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L29/00 , H01L23/52 , H01L23/48
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

4. 发明授权

US07839826B2 Method and apparatus to facilitate use of a session initiation protocol instance to support on-hold session status 有权
标题翻译：便利使用会话发起协议实例来支持持续会话状态的方法和装置
公开(公告)号：US07839826B2
公开(公告)日：2010-11-23
申请号：US11299429
申请日：2005-12-12
申请人： Edgardo L. Promenzio , Ajaykumar R. Idnani , Yi-Cheng Liu , Rajendra A. Panchal
发明人： Edgardo L. Promenzio , Ajaykumar R. Idnani , Yi-Cheng Liu , Rajendra A. Panchal
IPC分类号： H04W4/00
CPC分类号： H04L29/06027 , H04L65/1006 , H04L65/4007 , H04L67/14 , H04W36/14 , H04W76/10 , H04W76/22 , H04W80/10
摘要： During (101) a communication session for a plurality of user platforms wherein at least one of the user platforms is on hold and wherein the communication session is presently occurring in a first network and is terminable by a Session Initiation Protocol server as comprises a part of that first network, one establishes (102) in the first network a Session Initiation Protocol instance as corresponds to the communication session wherein the Session Initiation Protocol instance comprises, at least in part, session context information for the user platform that is on hold. Then, following a handoff of bearer support of the communication session from the first network to a second network, one uses (104) the Session Initiation Protocol instance to maintain the hold status of the user platform that is on hold with the Session Initiation Protocol server subsequent to the handoff such that the Session Initiation Protocol server does not terminate the communication session.
摘要翻译：在（101）期间，用于多个用户平台的通信会话，其中至少一个用户平台处于保持状态，并且其中通信会话当前正在第一网络中发生并且可由会话发起协议服务器终止，第一网络中，一个在第一网络中建立对应于通信会话的会话发起协议实例（102），其中会话发起协议实例至少部分地包括用于保持的用户平台的会话上下文信息。然后，在从第一网络到第二网络的通信会话的承载支持的切换之后，使用（104）会话发起协议实例来保持与会话发起协议服务器处于保持状态的用户平台的保持状态在切换之后，使得会话发起协议服务器不终止通信会话。

5. 发明授权

US07839174B2 Mixed-voltage tolerant I/O buffer and output buffer circuit thereof 有权
标题翻译：混合电压容限I / O缓冲器及其输出缓冲电路
公开(公告)号：US07839174B2
公开(公告)日：2010-11-23
申请号：US12330768
申请日：2008-12-09
申请人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
发明人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.
摘要翻译：输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。本文公开了混合电压输入/输出（I / O）缓冲器。

6. 发明申请

US20100141324A1 Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof 有权
标题翻译：混合电压容限I / O缓冲器和输出缓冲电路
公开(公告)号：US20100141324A1
公开(公告)日：2010-06-10
申请号：US12330768
申请日：2008-12-09
申请人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
发明人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.
摘要翻译：输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。本文公开了混合电压输入/输出（I / O）缓冲器。

7. 发明授权

US07607132B2 Process scheduling system and method 有权
标题翻译：流程调度系统和方法
公开(公告)号：US07607132B2
公开(公告)日：2009-10-20
申请号：US10820410
申请日：2004-04-08
申请人： Yi-Cheng Liu
发明人： Yi-Cheng Liu
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , Y02P90/20
摘要： A process scheduling system and method. The system includes a fetch module, a timing scheduling module and a trigger module. The fetch module fetches resource status data of at least one resource item of an application system periodically. The timing scheduling module dynamically determines an execution time point for at least one process according to the resource status data. The trigger module executes the process at the execution time point. The fetch module further fetches the resource status data as feedback for further determination after the process is executed.
摘要翻译：一种流程调度系统和方法。系统包括提取模块，定时调度模块和触发模块。获取模块周期性地获取应用系统的至少一个资源项的资源状态数据。定时调度模块根据资源状态数据动态确定至少一个进程的执行时间点。触发模块在执行时间点执行该过程。获取模块进一步获取资源状态数据作为反馈，以便在执行该过程之后进一步确定。

8. 发明申请

US20090068810A1 METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：金属氧化物半导体场效应晶体管的制备方法
公开(公告)号：US20090068810A1
公开(公告)日：2009-03-12
申请号：US12273517
申请日：2008-11-18
申请人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
发明人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L29/6656 , H01L29/66636 , H01L29/7834 , Y10S438/931 , Y10S438/933 , Y10S438/938
摘要： A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.
摘要翻译：制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。另外，源极/漏极层沉积在第二凹部中。由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

9. 发明申请

US20070133466A1 Method and apparatus to facilitate persistence of a handed-off communication system 有权
标题翻译：促进切换通信系统持久化的方法和装置
公开(公告)号：US20070133466A1
公开(公告)日：2007-06-14
申请号：US11299430
申请日：2005-12-12
申请人： Edgardo Promenzio , Ajaykumar Idnani , Yi-Cheng Liu , Rajendra Panchal
发明人： Edgardo Promenzio , Ajaykumar Idnani , Yi-Cheng Liu , Rajendra Panchal
IPC分类号： H04Q7/00
CPC分类号： H04L67/14 , H04W36/14 , H04W76/20 , H04W80/10
摘要： During a communication session (101) for a multi-network user platform (which communication session is presently occurring in a first network and is terminable by a Session Initiation Protocol server as comprises a part of that first network), one establishes (102) in the first network a Session Initiation Protocol instance as corresponds to the communication session. Thereafter, and particularly following a handoff of the communication session from the first network to a second network, one uses (104) the Session Initiation Protocol instance to maintain communications with the Session Initiation Protocol server such that the Session Initiation Protocol server does not terminate the communication session.
摘要翻译：在用于多网络用户平台（该通信会话当前正在第一网络中出现并且可由会话发起协议服务器终止为包括该第一网络的一部分）的通信会话（101）期间，建立（102）第一个网络会话发起协议实例对应于通信会话。此后，特别是在通信会话从第一网络切换到第二网络之后，使用（104）会话发起协议实例来维护与会话发起协议服务器的通信，使得会话发起协议服务器不终止沟通会话

10. 发明授权

US08207523B2 Metal oxide semiconductor field effect transistor with strained source/drain extension layer 有权
标题翻译：具有应变源极/漏极延伸层的金属氧化物半导体场效应晶体管
公开(公告)号：US08207523B2
公开(公告)日：2012-06-26
申请号：US11308718
申请日：2006-04-26
申请人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
发明人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
IPC分类号： H01L29/06 , H01L31/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L29/6656 , H01L29/66636 , H01L29/7834 , Y10S438/931 , Y10S438/933 , Y10S438/938
摘要： A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.
摘要翻译：公开了一种制造金属氧化物半导体场效应晶体管的方法。首先，设置形成有栅极结构的基板。之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹部。此外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。另外，源极/漏极层沉积在第二凹部中。由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

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