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1. 发明授权

US5946568A Self aligned method of fabricating a DRAM with improved capacitance 失效
标题翻译：制造具有改善电容的DRAM的自对准方法
公开(公告)号：US5946568A
公开(公告)日：1999-08-31
申请号：US649466
申请日：1996-05-17
申请人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
发明人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L28/82
摘要： A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved. The planar area of 2P can be increased by this method and not be limited by the overlap of 2C/3P.
摘要翻译：具有场板/ BL隔离工艺的自对准的DRAM芯片的固态存储器制造方法包括使用氧化物 - 多氧化物蚀刻，随后氧化或侧壁沉积（LPTEOS）来隔离场板和BL。该工艺在制造工艺中使用第一蚀刻剂和第二蚀刻剂来蚀刻BL / N +接触。在BL / N +接触蚀刻（2C蚀刻）期间，低选择性蚀刻剂首先蚀刻Ploy-3。该第一蚀刻剂应用大约一百八十秒。然后使用高Si选择性蚀刻剂进行第二蚀刻工艺，其蚀刻残余氧化物的方式。第二种蚀刻剂应用大约九十秒。侧壁上的暴露的聚合物通过氧化或沉积（LPTEOS）与接触孔隔离。在氧化过程中形成在衬底上的氧化物被各向异性腐蚀蚀刻掉。因此实现了BL / 3P的自对准。可以通过这种方法增加2P的平面面积，而不受2C / 3P的重叠的限制。

2. 发明授权

US07375027B2 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US07375027B2
公开(公告)日：2008-05-20
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置有保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

3. 发明授权

US07323729B2 Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor 有权
标题翻译：用于提高由含卤素前体及其产物形成的高温氧化物（HTO）的质量的方法及其设备
公开(公告)号：US07323729B2
公开(公告)日：2008-01-29
申请号：US11431087
申请日：2006-05-04
申请人： Zhong Dong , Chuck Jang , Chia-Shun Hsiao
发明人： Zhong Dong , Chuck Jang , Chia-Shun Hsiao
IPC分类号： H01L29/76
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/28158 , H01L21/3105 , H01L21/31612
摘要： A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.
摘要翻译：公开了一种方法和装置，用于降低通过化学气相沉积（CVD）形成的半导体氧化物组合物中的氯和/或其它结合的污染物的浓度，所述半导体氧化物组合物使用提供半导体元素的反应物如二氯硅烷（DCS）和氧提供反应物如N 2 O。在一个实施方案中，通过将N 2 O 2气体加热至约825℃至约950℃的温度来退火DCS-HTO膜，以引发放热分解 N 2 O气体并使加热的气体流过DCS-HTO膜，使得加热的N 2 O气体内的解离的原子氧自由基能够将分解能量转移到结合的氯原子上在DCS-HTO膜内，使得原子氧自由基可以填充DCS-HTO膜的半导体氧化物基质内的氧空位。可以用退火的DCS-HTO膜形成改进的ONO结构，用于浮动栅极或其他存储器应用中。

4. 发明申请

US20060079080A1 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US20060079080A1
公开(公告)日：2006-04-13
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

5. 发明授权

US07910429B2 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US07910429B2
公开(公告)日：2011-03-22
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

6. 发明授权

US07300745B2 Use of pedestals to fabricate contact openings 失效
标题翻译：使用基座制作接触孔
公开(公告)号：US07300745B2
公开(公告)日：2007-11-27
申请号：US10772520
申请日：2004-02-04
申请人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
发明人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L27/11539 , H01L27/115 , H01L27/11526
摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.
摘要翻译：非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。基座可以是虚拟结构。基座可以物理接触两个字线。

7. 发明申请

US20070187748A1 FLOATING GATE MEMORY STRUCTURES 审中-公开
标题翻译：浮动门记忆结构
公开(公告)号：US20070187748A1
公开(公告)日：2007-08-16
申请号：US11740698
申请日：2007-04-26
申请人： Chia-Shun Hsiao , Yi Ding
发明人： Chia-Shun Hsiao , Yi Ding
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , H01L29/42328 , H01L29/66825
摘要： Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.
摘要翻译：电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。然后沉积导电层以形成浮栅（410）。电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。结果，门耦合比增大。还提供其他功能。

8. 发明申请

US20070090409A1 Semiconductor device comprising an undoped oxide barrier 审中-公开
标题翻译：包括未掺杂氧化物屏障的半导体器件
公开(公告)号：US20070090409A1
公开(公告)日：2007-04-26
申请号：US11258119
申请日：2005-10-26
申请人： Chia-Shun Hsiao , Ming-Sheng Tung , Hong-Ming Chen , Ching-Hsien Huang
发明人： Chia-Shun Hsiao , Ming-Sheng Tung , Hong-Ming Chen , Ching-Hsien Huang
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/105 , H01L21/823456 , H01L27/1052
摘要： The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.
摘要翻译：本发明涉及一种半导体器件，其分别包括位于衬底的存储器阵列区域和外围电路区域中的至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度。半导体器件还包括位于存储器阵列区域和外围电路区域中的阻挡层，位于外围电路区域中的阻挡层上的未掺杂的氧化物屏障和含硼硅酸盐玻璃，其中位于存储器阵列区域中的阻挡层上和外围电路区域中未掺杂的氧化物屏障上。

9. 发明申请

US20060211255A1 Use of multiple etching steps to reduce lateral etch undercut 审中-公开
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20060211255A1
公开(公告)日：2006-09-21
申请号：US11432222
申请日：2006-05-10
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/302
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

10. 发明申请

US20050133828A1 Corner protection to reduce wrap around 有权
标题翻译：角落保护减少包裹
公开(公告)号：US20050133828A1
公开(公告)日：2005-06-23
申请号：US11048668
申请日：2005-01-31
申请人： Chia-Shun Hsiao , Dong Jun Kim
发明人： Chia-Shun Hsiao , Dong Jun Kim
IPC分类号： H01L21/311 , H01L21/762 , H01L21/8234 , H01L29/423 , H01L27/148 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/31111 , H01L21/823481 , H01L29/42368
摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.
摘要翻译：提供了一种方法和结构，其具有减少的栅极环绕，以有利地控制阈值电压并增加半导体器件的稳定性。提供与场介电层对准的间隔物，以在随后的蚀刻工艺期间保护电介质层。然后在随后形成栅极氧化物层和栅极导体层的一部分之前移除间隔物。有利地，间隔物保护场电介质的角区域，并且还允许靠近拐角的栅极氧化物的增强的厚度。

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