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1. 发明授权

US07375027B2 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US07375027B2
公开(公告)日：2008-05-20
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置有保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

2. 发明申请

US20060079080A1 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US20060079080A1
公开(公告)日：2006-04-13
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

3. 发明授权

US07297628B2 Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch 有权
标题翻译：通过调整用于电介质蚀刻的蚀刻掩模叠层来动态控制垂直接触直径的减小
公开(公告)号：US07297628B2
公开(公告)日：2007-11-20
申请号：US10718320
申请日：2003-11-19
申请人： Chunyuan Chao , Kuei-Chang Tsai , George A. Kovall
发明人： Chunyuan Chao , Kuei-Chang Tsai , George A. Kovall
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76816
摘要： Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.
摘要翻译：在设置在图案化光致抗蚀剂层下方的防反射涂层（ARC层）中产生向内锥形的开口。向内锥形开口的较小的底部宽度尺寸用于限定在ARC层下方设置的层间介质区域（ILD）中的另外的开口。在一个实施例中，ILD将集成电路的有源层集合与其第一主互连层分开。此外，在一个实施例中，锥形诱导蚀刻配方用于产生向内锥形的ARC开口，其中蚀刻配方使用CF4和CHF3的混合物，其中CF4 / CHF3体积流入比基本上小于5:1，更优选更接近1比1。

4. 发明申请

US20050106882A1 Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch 有权
标题翻译：通过调整用于电介质蚀刻的蚀刻掩模叠层来动态控制垂直接触直径的减小
公开(公告)号：US20050106882A1
公开(公告)日：2005-05-19
申请号：US10718320
申请日：2003-11-19
申请人： Chunyuan Chao , Kuei-Chang Tsai , George Kovall
发明人： Chunyuan Chao , Kuei-Chang Tsai , George Kovall
IPC分类号： H01L21/027 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76816
摘要： Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.
摘要翻译：在设置在图案化光致抗蚀剂层下方的防反射涂层（ARC层）中产生向内锥形的开口。向内锥形开口的较小的底部宽度尺寸用于限定在ARC层下方设置的层间介质区域（ILD）中的另外的开口。在一个实施例中，ILD将集成电路的有源层集合与其第一主互连层分开。此外，在一个实施例中，锥形诱导蚀刻配方用于产生向内锥形的ARC开口，其中蚀刻配方使用CF4和CHF3的混合物，其中CF4 / CHF3体积流入比基本上小于5:1，更优选更接近1比1。

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