专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050170646A1 Use of multiple etching steps to reduce lateral etch undercut 有权
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20050170646A1
公开(公告)日：2005-08-04
申请号：US10772932
申请日：2004-02-04
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/44 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

2. 发明申请

US20060211255A1 Use of multiple etching steps to reduce lateral etch undercut 审中-公开
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20060211255A1
公开(公告)日：2006-09-21
申请号：US11432222
申请日：2006-05-10
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/302
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

3. 发明申请

US20050170578A1 Use of pedestals to fabricate contact openings 失效
标题翻译：使用基座制作接触孔
公开(公告)号：US20050170578A1
公开(公告)日：2005-08-04
申请号：US10772520
申请日：2004-02-04
申请人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11539 , H01L27/115 , H01L27/11526
摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.
摘要翻译：非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。基座可以是虚拟结构。基座可以物理接触两个字线。

4. 发明授权

US07300745B2 Use of pedestals to fabricate contact openings 失效
标题翻译：使用基座制作接触孔
公开(公告)号：US07300745B2
公开(公告)日：2007-11-27
申请号：US10772520
申请日：2004-02-04
申请人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
发明人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L27/11539 , H01L27/115 , H01L27/11526
摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.
摘要翻译：非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。基座可以是虚拟结构。基座可以物理接触两个字线。

5. 发明授权

US07071115B2 Use of multiple etching steps to reduce lateral etch undercut 有权
公开(公告)号：US07071115B2
公开(公告)日：2006-07-04
申请号：US10772932
申请日：2004-02-04
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
IPC分类号： H01L21/302 , H01L21/461 , H01L21/44 , H01L21/76
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

6. 发明授权

US06566196B1 Sidewall protection in fabrication of integrated circuits 有权
标题翻译：集成电路制造中的侧壁保护
公开(公告)号：US06566196B1
公开(公告)日：2003-05-20
申请号：US10146979
申请日：2002-05-15
申请人： Barbara Haselden , Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Chung Wai Leung , Kuei-Chang Tsai
发明人： Barbara Haselden , Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Chung Wai Leung , Kuei-Chang Tsai
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , Y10S438/954
摘要： In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.
摘要翻译：在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。因此，可以用各向同性蚀刻去除氮化硅。因此，减小了对衬底隔离电介质（210）的潜在损害。还提供了其他实施例。

7. 发明申请

US20050287762A1 Formation of removable shroud by anisotropic plasma etch 失效
标题翻译：通过各向异性等离子体蚀刻形成可拆卸护罩
公开(公告)号：US20050287762A1
公开(公告)日：2005-12-29
申请号：US10877591
申请日：2004-06-25
申请人： John Lee , Barbara Haselden
发明人： John Lee , Barbara Haselden
IPC分类号： H01L21/28 , H01L21/311 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8234
CPC分类号： H01L21/28238 , H01L21/28123 , H01L21/31138 , H01L21/31144 , H01L21/76224 , H01L21/823481
摘要： Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an O2 plus Cl2 plasma and/or bias power during the plasma etch is used as a tuning parameter.
摘要翻译：与STI晶片中的沟槽填充步骤相邻的牺牲氧化物的各向同性蚀刻可导致沟槽填充材料的侧壁（例如，HDP氧化物）的不希望的蚀刻。侧壁保护方法使用沟槽填充步骤和牺牲氧化物与耐蚀刻碳水化合物一致地涂覆。在一个实施例中，将适合的ARC流体旋转并硬化。选择性，干燥的等离子体在牺牲氧化物上蚀刻硬化的ARC，同时留下附着到沟槽填充侧壁的ARC的完整部分。残余侧壁材料限定了保护罩，其延伸随后的各向同性蚀刻剂（例如，湿HF溶液）从即将到达沟槽填充材料的侧壁。可以通过调整回蚀配方来控制护罩的延迟长度。在一个实施例中，在等离子体蚀刻期间，O 2 O 2 + Cl 2等离子体中的氧含量和/或偏置功率用作调谐参数。

8. 发明授权

US06933218B1 Low temperature nitridation of amorphous high-K metal-oxide in inter-gates insulator stack 有权
标题翻译：在栅极绝缘体堆叠中的非晶高K金属氧化物的低温氮化
公开(公告)号：US06933218B1
公开(公告)日：2005-08-23
申请号：US10866380
申请日：2004-06-10
申请人： Tai-Peng Lee , Barbara Haselden
发明人： Tai-Peng Lee , Barbara Haselden
IPC分类号： H01L21/28 , H01L21/314 , H01L21/3205 , H01L29/51
CPC分类号： H01L21/28273 , H01L21/3143 , H01L29/511
摘要： An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal oxide with a low temperature plasma treatment that maintains temperature below the recrystallization temperature of the amorphous material. Such a plasma treatment has been found to improve breakdown voltage characteristics of the insulator. In one embodiment, the metal oxide includes aluminum oxide and it is fluorinated with low temperature plasma prior to nitridation.
摘要翻译：通过在硅系绝缘体（例如，氧化硅层）上形成非晶质金属氧化物层来定义OXO型多晶硅绝缘体（其中X为高K金属氧化物，O为绝缘氧化物），然后用低温等离子体处理将至少上述非晶金属氧化物的上层和下层亚层氮化，该低温等离子体处理将温度维持在非晶材料的再结晶温度以下。已经发现这种等离子体处理改善了绝缘体的击穿电压特性。在一个实施方案中，金属氧化物包括氧化铝，并且在氮化之前用低温等离子体氟化。

9. 发明授权

US07737487B2 Nonvolatile memories with tunnel dielectric with chlorine 有权
标题翻译：带有隧道电介质的非易失性存储器
公开(公告)号：US07737487B2
公开(公告)日：2010-06-15
申请号：US12134834
申请日：2008-06-06
申请人： Zhong Dong , Barbara Haselden
发明人： Zhong Dong , Barbara Haselden
IPC分类号： G11C11/34 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.
摘要翻译：在具有电荷捕获电介质（150）的非易失性存储单元中，隧道电介质（140）包括邻近电荷捕获电介质的氯，而与电池的沟道区（120）相邻的氯不含氯（或更少的氯）。与电荷捕获介质相邻的氯用于改善编程和/或擦除速度。与通道区相邻的低氯浓度防止氯降解数据保留。还提供其他功能。

10. 发明申请

US20070155189A1 Use of TEOS oxides in integrated circuit fabrication processes 失效
标题翻译：在集成电路制造工艺中使用TEOS氧化物
公开(公告)号：US20070155189A1
公开(公告)日：2007-07-05
申请号：US11326547
申请日：2006-01-04
申请人： Tai-Peng Lee , Barbara Haselden
发明人： Tai-Peng Lee , Barbara Haselden
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L21/02164 , H01L21/02203 , H01L21/02274 , H01L21/31111 , H01L21/31695
摘要： A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.
摘要翻译：提供一种制造用于图案化和蚀刻的低温可去除二氧化硅硬掩模的方法，其中使用四乙基邻 - 硅烷（TEOS）沉积二氧化硅硬掩模。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式