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1. 发明授权

US6156654A Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices 失效
标题翻译：用于在二分之一微米器件中制造超薄硅化物的脉冲激光硫化
公开(公告)号：US6156654A
公开(公告)日：2000-12-05
申请号：US206746
申请日：1998-12-07
申请人： Chaw Sing Ho , Yuan Ping Lee , Chan Lap , Yong Feng Lu , R. P.G. Karunasiri
发明人： Chaw Sing Ho , Yuan Ping Lee , Chan Lap , Yong Feng Lu , R. P.G. Karunasiri
IPC分类号： H01L21/268 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L29/66628 , H01L21/268 , H01L21/28518 , H01L29/665 , H01L21/28052
摘要： Methods are disclosed for forming ultra-thin (.about.300-.ANG.), uniform and stoichiometric C54-titanium silicide with a Ti film thickness of 200-300 .ANG. using pulsed laser salicidation. The invention achieves this by preferably step-scanning from die to die, across the wafer using laser pulses with an optical fluence (laser energy) ranging from 0.1 to 0.2 J/cm.sup.2 for approximately 23 nanoseconds per pulse. The source of radiation can be a XeCl or KrF excimer laser, or one in which the laser's wavelength is chosen such that the laser energy is absorbed the most by the refractory metal, i.e. titanium (Ti), cobalt (Co) or nickel (Ni). The laser beam size is typically die-size or can be fine tuned to 1 to 100 .mu.m and can be optimized to reduce the intensity variation across the laser spot diameter. At each position between 1 to 100 pulses can be emitted on the wafer. Localized heating is possible with the ability to establish the ambient temperature at or below 200.degree. C.
摘要翻译：公开了使用脉冲激光盐析法形成超薄（DIFFERENCE 300-ANGSTROM），均匀和化学计量的C54-硅化钛，Ti膜厚度为200-300安培的方法。本发明通过优选地使用具有0.1至0.2J / cm 2的光能（激光能量）的脉冲，每脉冲约23纳秒的激光脉冲，优选地通过晶片将晶片从芯片到裸片逐步扫描。辐射源可以是XeCl或KrF准分子激光器，或者其中选择激光器的波长使得激光能量被难熔金属，即钛（Ti），钴（Co）或镍（Ni ）。激光束尺寸通常是模具尺寸或可以微调到1至100μm，并且可以被优化以减少激光光斑直径上的强度变化。在晶片上可以发射1至100个脉冲的每个位置。局部加热是可能的，能够建立环境温度在或低于200℃。

2. 发明授权

US06281117B1 Method to form uniform silicide features 失效
标题翻译：形成均匀硅化物特征的方法
公开(公告)号：US06281117B1
公开(公告)日：2001-08-28
申请号：US09425994
申请日：1999-10-25
申请人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
发明人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , Y10S977/859
摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.
摘要翻译：描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。金属层沉积在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

3. 发明授权

US06528838B1 Damascene MIM capacitor with a curvilinear surface structure 有权
标题翻译：具有曲面表面结构的大马士革MIM电容器
公开(公告)号：US06528838B1
公开(公告)日：2003-03-04
申请号：US10012296
申请日：2001-11-13
申请人： Chit Hwei Ng , Chaw Sing Ho
发明人： Chit Hwei Ng , Chaw Sing Ho
IPC分类号： H01L27108
CPC分类号： H01L28/82 , H01L28/55
摘要： In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.
摘要翻译：在一个方法实施例中，本发明在镶嵌工艺期间背景在衬底中形成开口。本实施例然后在镶嵌过程期间至少部分地在开口内形成具有彼此相对的两个曲线表面的电介质区域。表面相对于水平横截面是曲线的。然后，本实施例在镶嵌过程期间形成具有靠近电介质区域的一个表面的曲线表面的第一铜区域。然后，本实施例在镶嵌过程期间叙述形成具有靠近电介质区域的第二表面的曲线表面的第二铜区域。这样，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，从而形成垂直圆柱形MIM电容器。

4. 发明授权

US6010954A Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices 失效
标题翻译： Cmos门结构，用于将0.1％以上设备的自杀过程整合
公开(公告)号：US6010954A
公开(公告)日：2000-01-04
申请号：US156359
申请日：1998-09-18
申请人： Chaw Sing Ho , R. P. G. Karunasiri , Soo Jin Chua , Kin Leong Pey , Kong Hean Lee
发明人： Chaw Sing Ho , R. P. G. Karunasiri , Soo Jin Chua , Kin Leong Pey , Kong Hean Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L21/18 , H01L21/283 , H01L21/335 , H01L21/461
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/66545
摘要： A method to form a "mushroom shaped" gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22. Source/drain regions 54 are formed. A salicide process forms silicide source/drain contacts 64 and forms extra large silicided gate contacts 70 to reduce parasitic resistance.
摘要翻译：形成增加顶栅硅化物接触面积并改善自对准硅化物工艺的“蘑菇形”门结构18 22 44A 70的方法，特别是TiSi 2自对准硅化物。新颖的上部栅极延伸部分44A增加了顶部栅极表面积，使得硅化物栅极接触70将具有低电阻率。本发明包括形成由栅极氧化物层18，中心栅极部分22和硬掩模26组成的栅极堆叠18 22 26.接下来，我们在栅极叠层22 26上形成第一绝缘层40.硬掩模26 并且去除第一绝缘层40的第一厚度以暴露中心栅极部分22的侧壁。第二导电层44形成在第一绝缘层46和中心栅极部分22上。第二导电层44被蚀刻到在中心栅极部分22的侧壁上形成关键的圆形上部栅极延伸部分44A。下部矩形侧壁间隔件52形成在中心栅极部分22的侧壁上。形成源极/漏极区域54。自对准硅化物工艺形成硅化物源极/漏极触点64并形成特大的硅化物栅极触点70以减小寄生电阻。

5. 发明申请

US20140374812A1 DEVICE INCLUDING ACTIVE FLOATING GATE REGION AREA THAT IS SMALLER THAN CHANNEL AREA 有权
标题翻译：包括主要浮动门区域的设备比通道区域小
公开(公告)号：US20140374812A1
公开(公告)日：2014-12-25
申请号：US14375695
申请日：2012-04-30
申请人： Ning Ge , Adam L. Ghozeil , Chaw Sing Ho , Trudy Benjamin
发明人： Ning Ge , Adam L. Ghozeil , Chaw Sing Ho , Trudy Benjamin
IPC分类号： H01L27/115 , H01L29/66 , H01L21/288 , H01L29/10 , H01L21/3213 , H01L21/28 , H01L29/788 , H01L29/423
CPC分类号： H01L27/11517 , G11C16/0425 , H01L21/28158 , H01L21/288 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L27/1156 , H01L29/1033 , H01L29/42324 , H01L29/66825 , H01L29/7881 , H01L29/7884
摘要： A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.
摘要翻译：一种包括漏极，沟道，浮动栅极和控制栅极的器件。通道围绕排水沟并具有通道区域。浮置栅极包括具有有源浮栅区域的有源浮栅区域。控制栅极经由控制电容耦合到有源浮栅区域，其中有源浮栅区域小于沟道区域。

6. 发明授权

US06902981B2 Structure and process for a capacitor and other devices 有权
标题翻译：电容器和其他器件的结构和工艺
公开(公告)号：US06902981B2
公开(公告)日：2005-06-07
申请号：US10268315
申请日：2002-10-10
申请人： Chit Hwei Ng , Chaw Sing Ho
发明人： Chit Hwei Ng , Chaw Sing Ho
IPC分类号： H01L21/02 , H01L27/06 , H01L27/08 , H01L21/20 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0682 , H01L27/0805 , H01L28/40
摘要： A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section. The first portion and the first section can form resistors, capacitors or other devices.
摘要翻译：通过提供半导体结构并在半导体结构上提供顶部绝缘层和导电特征来制造电容器和其它器件的结构和方法; 在顶部绝缘层上形成第一导电层; 图案化第一导电层以形成至少电容器底板和第一导电层的第一部分; 在顶部绝缘层和电容器底板和第一导电层的第一部分上形成电容器电介质层; 在所述电容器介电层上形成第二导电层; 以及图案化所述第二导电层以在所述底板上形成至少顶板和在所述电容器电介质层上形成所述第二导电层的第一部分。该实施例还可以包括顶层绝缘层中的导电特征，其可以位于底板，第一部分或/和第一部分的下面。第一部分和第一部分可以形成电阻器，电容器或其他装置。

7. 发明授权

US06645810B2 Method to fabricate MIM capacitor using damascene process 失效
标题翻译：使用镶嵌工艺制造MIM电容器的方法
公开(公告)号：US06645810B2
公开(公告)日：2003-11-11
申请号：US10012292
申请日：2001-11-13
申请人： Chit Hwei Ng , Chaw Sing Ho
发明人： Chit Hwei Ng , Chaw Sing Ho
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L21/768 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.
摘要翻译：在一个实施例中，本发明叙述在第一衬底中形成多个第一开口。然后，本实施例在镶嵌工艺期间在每个第一开口内形成铜区，其中每个铜区具有顶表面。然后，本实施例在镶嵌过程期间将电介质层布置成靠近每个第一铜区域的顶表面。在电介质上沉积第二衬底之后，制成第二衬底中的多个第二开口。接下来，在镶嵌工艺期间，在第二开口中形成多个第二铜区。因此，电介质区域设置在第一铜区域和第二铜区域之间。在这样做时，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，使得在镶嵌工艺期间形成金属 - 绝缘体 - 金属（MIM）电容器。

8. 发明授权

US06624040B1 Self-integrated vertical MIM capacitor in the dual damascene process 有权
标题翻译：自组装垂直MIM电容器在双镶嵌工艺中
公开(公告)号：US06624040B1
公开(公告)日：2003-09-23
申请号：US10251350
申请日：2002-09-20
申请人： Chit Hwei Ng , Chaw Sing Ho , John E. Martin
发明人： Chit Hwei Ng , Chaw Sing Ho , John E. Martin
IPC分类号： H01L2176
CPC分类号： H01L23/5223 , H01L21/76811 , H01L27/0805 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process is described. A first dual damascene opening and a pair of second dual damascene openings are provided in a first dielectric layer overlying a substrate. The first and second dual damascene openings are filled with a first copper layer wherein the filled first dual damascene opening forms a logic interconnect and the filled pair of second dual damascene openings forms a pair of capacitor electrodes. The first dielectric layer is etched away between the pair of capacitor electrodes leaving a space between the pair of capacitor electrodes. The space between the pair of capacitor electrodes is filled with a high dielectric constant material to complete fabrication of a vertical MIM capacitor in the fabrication of an integrated circuit device. The fabrication of the capacitor can begin at any metal layer. The process of the invention can be extended to form a parallel capacitor, a series capacitor, stacked capacitors, and so on.
摘要翻译：描述了使用集成铜双镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。在衬底上的第一电介质层中设置有第一双镶嵌开口和一对第二双镶嵌开口。第一和第二双镶嵌开口填充有第一铜层，其中填充的第一双镶嵌开口形成逻辑互连，并且填充的一对第二双镶嵌开口形成一对电容器电极。在一对电容器电极之间蚀刻第一介电层，留下一对电容器电极之间的空间。一对电容器电极之间的空间填充有高介电常数材料，以在集成电路器件的制造中完成纵向MIM电容器的制造。电容器的制造可以从任何金属层开始。本发明的方法可以扩展成并联电容器，串联电容器，堆叠电容器等。

9. 发明授权

US09252149B2 Device including active floating gate region area that is smaller than channel area 有权
标题翻译：器件包括有源浮栅区域小于通道面积
公开(公告)号：US09252149B2
公开(公告)日：2016-02-02
申请号：US14375695
申请日：2012-04-30
申请人： Ning Ge , Adam L. Ghozeil , Chaw Sing Ho , Trudy Benjamin
发明人： Ning Ge , Adam L. Ghozeil , Chaw Sing Ho , Trudy Benjamin
IPC分类号： H01L27/115 , H01L29/788 , G11C16/04 , H01L21/28 , H01L21/288 , H01L21/3213 , H01L29/10 , H01L29/423 , H01L29/66
CPC分类号： H01L27/11517 , G11C16/0425 , H01L21/28158 , H01L21/288 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L27/1156 , H01L29/1033 , H01L29/42324 , H01L29/66825 , H01L29/7881 , H01L29/7884
摘要： A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.
摘要翻译：一种包括漏极，沟道，浮动栅极和控制栅极的器件。通道围绕排水沟并具有通道区域。浮置栅极包括具有有源浮栅区域的有源浮栅区域。控制栅极经由控制电容耦合到有源浮栅区域，其中有源浮栅区域小于沟道区域。

10. 发明授权

US06730573B1 MIM and metal resistor formation at CU beol using only one extra mask 有权
标题翻译： MIM和金属电阻器形成在CU beol仅使用一个额外的掩模
公开(公告)号：US06730573B1
公开(公告)日：2004-05-04
申请号：US10286257
申请日：2002-11-01
申请人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
发明人： Chit Hwei Ng , Chaw Sing Ho , Lup San Leong , Shao Kai , Raymond Jacob Joy , Sanford Chu , Sajan Marokkey Raphael
IPC分类号： H01L2120
CPC分类号： H01L28/24 , H01L21/76838 , H01L23/5223 , H01L23/5228 , H01L23/5252 , H01L23/5329 , H01L27/0682 , H01L27/0805 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make
摘要翻译：已经开发了使用单镶嵌或双镶嵌加工制造同时高容量，小于0.13微米的金属 - 绝缘体 - 金属电容器，金属电阻器和金属互连的改进方法。关键的优点是同时使用一个额外的掩模掩模版同时形成MIM电容和电阻。克服了BEOL后端存在的几个当前的障碍，即：（a）使用两个或更多个光掩膜使<0.13μm的MIM电容器，（b）凹凸的铜表面，当电介质直接沉积时（c）当在底部MIM板层上尝试蚀刻停止时，（c）蚀刻期间的颗粒产生问题，最后，（d）在需要大的铜MIM板时发生CMP期间的凹陷，随后的电容匹配问题。该集成方法克服了上述障碍，同时使用镶嵌处理形成MIM电容器，金属电阻器和金属互连。此外，本文所述的形成MIM电容器的方法也可用于在现场可编程门阵列FPGA中形成反熔丝器件。

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