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1. 发明申请

US20130025483A1 SUBSTRATE TREATMENT APPARATUS, PRINTERS, AND METHODS TO TREAT A PRINT SUBSTRATE 审中-公开
标题翻译：基板处理设备，打印机和处理打印基板的方法
公开(公告)号：US20130025483A1
公开(公告)日：2013-01-31
申请号：US13194367
申请日：2011-07-29
申请人： Omer Gila , Daihua Zhang , Thomas C. Anthony , Hou Tee Ng
发明人： Omer Gila , Daihua Zhang , Thomas C. Anthony , Hou Tee Ng
IPC分类号： B41K1/22
CPC分类号： B41J11/0015 , B05C1/0817 , B05C1/0834 , B41F9/10 , B41F9/1072 , B41F23/00 , B41M5/0017 , B41M7/0018
摘要： Substrate treatment apparatus, printers, and methods to treat a print substrate are disclosed. An example apparatus includes a first roller to receive a treatment fluid from a reservoir, a blade to adjust an amount of the treatment fluid present on the first roller, and a second roller to receive an adjusted amount of the treatment fluid from the first roller and to apply the treatment fluid to a substrate, the treatment fluid applied to the substrate to result in a layer of treatment fluid less than about 0.4 micrometers thick on the substrate.
摘要翻译：公开了用于处理印刷基板的基板处理设备，打印机和方法。示例性设备包括：第一辊，用于从储存器接收处理流体;叶片，用于调节存在于第一辊上的处理流体的量;以及第二辊，用于接收来自第一辊的调节量的处理流体;以及将处理流体施加到基底上，将处理流体施加到基底上以在基底上产生小于约0.4微米厚的处理流体层。

2. 发明授权

US07718545B1 Fabrication process 失效
标题翻译：制造工艺
公开(公告)号：US07718545B1
公开(公告)日：2010-05-18
申请号：US11590372
申请日：2006-10-30
申请人： Hou Tee Ng , Alfred I-Tsung Pan
发明人： Hou Tee Ng , Alfred I-Tsung Pan
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L27/11568 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L29/66742
摘要： A fabrication process, including forming one or more layers on at least a sidewall of a topographical feature of a substantially planar substrate, the sidewall being substantially orthogonal to the substrate; and planarizing respective portions of the one or more layers to form a planar surface substantially parallel to the substrate, wherein the planar surface includes respective co-planar surfaces of the one or more layers, at least one of the surfaces having a dimension determined by a thickness of the corresponding layer.
摘要翻译：一种制造方法，包括在基本平坦的基底的形貌特征的至少一个侧壁上形成一个或多个层，所述侧壁基本上垂直于所述基底; 以及平坦化所述一个或多个层的相应部分以形成基本上平行于所述基底的平坦表面，其中所述平坦表面包括所述一个或多个层的相应共平面表面，所述表面中的至少一个具有由相应层的厚度。

3. 发明授权

US06696761B2 Method to encapsulate copper plug for interconnect metallization 有权
标题翻译：封装用于互连金属化的铜插头的方法
公开(公告)号：US06696761B2
公开(公告)日：2004-02-24
申请号：US09785108
申请日：2001-02-20
申请人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
IPC分类号： H01L2348
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76879 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.
摘要翻译：掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。塞孔部分地填充有无电沉积的铜金属塞。封装金属沉积物对插头进行覆盖，而不会发生任何中间氧化和降解。在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化器件实现金属层与绝缘体层的形貌的共面性。

4. 发明授权

US06495200B1 Method to deposit a seeding layer for electroless copper plating 有权
标题翻译：沉积用于化学镀铜的接种层的方法
公开(公告)号：US06495200B1
公开(公告)日：2002-12-17
申请号：US09206733
申请日：1998-12-07
申请人： Lap Chan , Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Fong Yau Li , Hou Tee Ng
IPC分类号： B05D512
CPC分类号： H01L21/76849 , C23C18/1607 , C23C18/1689 , H01L21/288 , H01L21/76843 , H01L21/76874
摘要： A method of for electroless copper deposition using a Pd/Pd acetate seeding layer formed in using only two components (Pd acetate and solvent) to form an interconnect for a semiconductor device. The invention has two preferred embodiments. The first embodiment forms a Key seed layer composed of Pd/Pd acetate by a spin-on or dip process for the electroless plating of a Cu plug. The second embodiment forms a Pd passivation cap layer over the Cu plug to prevent the Cu plug from oxidizing.
摘要翻译：使用仅使用两种组分（Pd醋酸盐和溶剂）形成的Pd / Pd乙酸盐接种层来形成半导体器件的互连的无电镀铜沉积的方法。本发明具有两个优选实施例。第一实施例通过用于铜插塞的无电镀的旋涂或浸渍方法形成由Pd / Pd乙酸盐构成的键种子层。第二实施例在Cu插塞上形成Pd钝化帽层以防止Cu插塞氧化。

5. 发明申请

US20080024752A1 Contact printing oxide-based electrically active micro-features 失效
标题翻译：接触印刷氧化物基电活性微特征
公开(公告)号：US20080024752A1
公开(公告)日：2008-01-31
申请号：US11496939
申请日：2006-07-31
申请人： Hou Tee Ng , Alfred I-Tsung Pan
发明人： Hou Tee Ng , Alfred I-Tsung Pan
IPC分类号： G03B27/02
CPC分类号： G03B27/02
摘要： Contact printing can be used to form electrically active micro-features on a substrate. An ink formulation containing an oxide precursor is used to form the micro-features, which are heat cured to form oxides. Various precursors are illustrated which can be used to form conducting, insulating, and semiconductor micro-features.
摘要翻译：接触印刷可用于在基材上形成电活性微特征。使用含有氧化物前体的油墨制剂形成微特征，其被热固化以形成氧化物。示出了可用于形成导电，绝缘和半导体微特征的各种前体。

6. 发明授权

US08029852B2 Contact printing oxide-based electrically active micro-features 失效
标题翻译：接触印刷氧化物基电活性微特征
公开(公告)号：US08029852B2
公开(公告)日：2011-10-04
申请号：US11496939
申请日：2006-07-31
申请人： Hou Tee Ng , Alfred I-Tsung Pan
发明人： Hou Tee Ng , Alfred I-Tsung Pan
IPC分类号： G03B27/02
CPC分类号： G03B27/02
摘要： Contact printing can be used to form electrically active micro-features on a substrate. An ink formulation containing an oxide precursor is used to form the micro-features, which are heat cured to form oxides. Various precursors are illustrated which can be used to form conducting, insulating, and semiconductor micro-features.
摘要翻译：接触印刷可用于在基材上形成电活性微特征。使用含有氧化物前体的油墨制剂形成微特征，其被热固化以形成氧化物。示出了可用于形成导电，绝缘和半导体微特征的各种前体。

7. 发明授权

US6136693A Method for planarized interconnect vias using electroless plating and CMP 失效
标题翻译：使用化学镀和CMP的平面化互连通孔的方法
公开(公告)号：US6136693A
公开(公告)日：2000-10-24
申请号：US958427
申请日：1997-10-27
申请人： Lap Chan , Hou Tee Ng
发明人： Lap Chan , Hou Tee Ng
IPC分类号： C23C14/58 , C23C16/56 , C23C18/30 , C23C18/40 , H01L21/768 , B05D5/12 , C23C14/32 , H01L21/4763
CPC分类号： C23C14/588 , C23C16/56 , C23C18/30 , C23C18/405 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76874 , H01L21/76879
摘要： An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
摘要翻译：已经开发了用于在半导体集成电路中的导电互连图案的连续层之间制造导电通孔的改进和新的方法。该方法利用第一CMP步骤形成屏障衬里的接触孔，通过化学镀将铜沉积到屏障衬里接触孔中，以及第二CMP步骤以去除铜的过度生长，从而产生铜表面和周围绝缘体之间的共面性表面。

8. 发明授权

US07217650B1 Metallic nanowire interconnections for integrated circuit fabrication 失效
标题翻译：用于集成电路制造的金属纳米线互连
公开(公告)号：US07217650B1
公开(公告)日：2007-05-15
申请号：US10816576
申请日：2004-03-24
申请人： Hou Tee Ng , Jun Li , Meyya Meyyappan
发明人： Hou Tee Ng , Jun Li , Meyya Meyyappan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/842 , Y10S977/843 , H01L2924/00
摘要： A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.
摘要翻译：一种用于在两个或多个电气部件之间制造电互连的方法。导电层设置在基体上，薄的图案化催化剂阵列沉积在导电层的暴露表面上。在催化剂阵列周围提供金属纳米线（MeNW）的金属前体的气体或蒸汽，并且MeNWs在导电层和催化剂阵列之间生长。除去催化剂阵列和每个MeNW的一部分以提供MeNW的暴露端。

9. 发明授权

US06660636B1 Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating 失效
标题翻译：高选择性和完整的互连金属线和通孔/接触孔通过化学镀填充
公开(公告)号：US06660636B1
公开(公告)日：2003-12-09
申请号：US09743675
申请日：2001-03-09
申请人： Sam Fong Yau Li , Hou Tee Ng
发明人： Sam Fong Yau Li , Hou Tee Ng
IPC分类号： H01L21302
CPC分类号： H01L21/76877 , H01L21/288 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A novel method for the activation of semiconductor substrates for highly selective electroless copper plating in multilayer interconnect metallization lines and vias/contact holes has been developed. A copper-seeded polysilicon layer is provided over the substrate to facilitate growth of copper into the vias. Subsequent rinsing and chemical-mechanical polishing processes allow removal of overgrowth of copper and the polysilicon layer to achieve overall smooth topography of the copper surface and the insulating layer surface of the substrate.
摘要翻译：已经开发了用于激活用于多层互连金属化线和通孔/接触孔中的高选择性化学镀铜的半导体衬底的新颖方法。铜基种子多晶硅层设置在衬底上，以促进铜进入通孔。随后的漂洗和化学机械抛光工艺允许去除铜和多晶硅层的过度生长，以实现铜表面和衬底的绝缘层表面的总体光滑的形貌。

10. 发明授权

US06281117B1 Method to form uniform silicide features 失效
标题翻译：形成均匀硅化物特征的方法
公开(公告)号：US06281117B1
公开(公告)日：2001-08-28
申请号：US09425994
申请日：1999-10-25
申请人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
发明人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , Y10S977/859
摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.
摘要翻译：描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。金属层沉积在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

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