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1. 发明授权

US06281117B1 Method to form uniform silicide features 失效
标题翻译：形成均匀硅化物特征的方法
公开(公告)号：US06281117B1
公开(公告)日：2001-08-28
申请号：US09425994
申请日：1999-10-25
申请人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
发明人： Lap Chan , Chaw Sing Ho , Fong Yau Sam Li , Hou Tee Ng
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , Y10S977/859
摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.
摘要翻译：描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。金属层沉积在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

2. 发明授权

US06180501B2 Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process 失效
标题翻译：制造二分之一微米自对准钛硅化物工艺的双多晶硅栅极结构的方法
公开(公告)号：US06180501B2
公开(公告)日：2001-01-30
申请号：US09418036
申请日：1999-10-14
申请人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
发明人： Kin-Leong Pey , Chaw Sing Ho , Lap Chan
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28035 , H01L21/28052 , H01L21/28518 , H01L29/4925 , H01L29/4933 , H01L29/66545
摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.
摘要翻译：本发明涉及集成电路器件的制造，更具体地说，涉及一种使硅化多晶硅栅极用于制造窄沟道CMOS器件时可能出现的局部机械应力问题最小化的方法。本发明解决了避免多晶硅栅极中的典型的应力引起的问题，例如不均匀的硅化物（包括弯曲，变薄边缘等）和空隙，随着栅极长度的不断减小，这些问题变得越来越严重。本发明的关键是在狭窄的硅化物栅极中，在较大的垂直表面积上传播高度有害的机械应力。这是通过使用用于栅极的薄/厚双重多晶硅堆叠实现的，由此，下部薄多晶硅栅极层不被硅化，并且随后硅化上部厚多晶硅层。在有源源极 - 漏极区域的硅化期间，使用绝缘层来防止下部薄多晶硅栅极的硅化。同样的绝缘层也用于通过在用于间隔物形成的干蚀刻期间保护下部薄多晶硅栅极层的表面晶界不被聚合物填充而避免机械应力的另一个原因。高堆叠栅极结构允许硅化物引起的应力更安全地远离有源器件。

3. 发明授权

US06696761B2 Method to encapsulate copper plug for interconnect metallization 有权
标题翻译：封装用于互连金属化的铜插头的方法
公开(公告)号：US06696761B2
公开(公告)日：2004-02-24
申请号：US09785108
申请日：2001-02-20
申请人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
IPC分类号： H01L2348
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76879 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.
摘要翻译：掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。塞孔部分地填充有无电沉积的铜金属塞。封装金属沉积物对插头进行覆盖，而不会发生任何中间氧化和降解。在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化器件实现金属层与绝缘体层的形貌的共面性。

4. 发明授权

US06495200B1 Method to deposit a seeding layer for electroless copper plating 有权
标题翻译：沉积用于化学镀铜的接种层的方法
公开(公告)号：US06495200B1
公开(公告)日：2002-12-17
申请号：US09206733
申请日：1998-12-07
申请人： Lap Chan , Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Fong Yau Li , Hou Tee Ng
IPC分类号： B05D512
CPC分类号： H01L21/76849 , C23C18/1607 , C23C18/1689 , H01L21/288 , H01L21/76843 , H01L21/76874
摘要： A method of for electroless copper deposition using a Pd/Pd acetate seeding layer formed in using only two components (Pd acetate and solvent) to form an interconnect for a semiconductor device. The invention has two preferred embodiments. The first embodiment forms a Key seed layer composed of Pd/Pd acetate by a spin-on or dip process for the electroless plating of a Cu plug. The second embodiment forms a Pd passivation cap layer over the Cu plug to prevent the Cu plug from oxidizing.
摘要翻译：使用仅使用两种组分（Pd醋酸盐和溶剂）形成的Pd / Pd乙酸盐接种层来形成半导体器件的互连的无电镀铜沉积的方法。本发明具有两个优选实施例。第一实施例通过用于铜插塞的无电镀的旋涂或浸渍方法形成由Pd / Pd乙酸盐构成的键种子层。第二实施例在Cu插塞上形成Pd钝化帽层以防止Cu插塞氧化。

5. 发明授权

US6136693A Method for planarized interconnect vias using electroless plating and CMP 失效
标题翻译：使用化学镀和CMP的平面化互连通孔的方法
公开(公告)号：US6136693A
公开(公告)日：2000-10-24
申请号：US958427
申请日：1997-10-27
申请人： Lap Chan , Hou Tee Ng
发明人： Lap Chan , Hou Tee Ng
IPC分类号： C23C14/58 , C23C16/56 , C23C18/30 , C23C18/40 , H01L21/768 , B05D5/12 , C23C14/32 , H01L21/4763
CPC分类号： C23C14/588 , C23C16/56 , C23C18/30 , C23C18/405 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76874 , H01L21/76879
摘要： An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
摘要翻译：已经开发了用于在半导体集成电路中的导电互连图案的连续层之间制造导电通孔的改进和新的方法。该方法利用第一CMP步骤形成屏障衬里的接触孔，通过化学镀将铜沉积到屏障衬里接触孔中，以及第二CMP步骤以去除铜的过度生长，从而产生铜表面和周围绝缘体之间的共面性表面。

6. 发明授权

US06214728B1 Method to encapsulate copper plug for interconnect metallization 有权
标题翻译：封装用于互连金属化的铜插头的方法
公开(公告)号：US06214728B1
公开(公告)日：2001-04-10
申请号：US09196604
申请日：1998-11-20
申请人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
发明人： Lap Chan , Sam Fong Yau Li , Hou Tee Ng
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76879 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.
摘要翻译：掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。塞孔部分地填充有无电沉积的铜金属塞。封装金属沉积物覆盖插塞，而不会发生任何中间氧化和降解。在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化器件实现金属层与绝缘体层的形貌的共面性。

7. 发明授权

US09262732B2 System and method of enterprise action item planning, executing, tracking and analytics 有权
标题翻译：企业行动项目计划，执行，跟踪和分析的系统和方法
公开(公告)号：US09262732B2
公开(公告)日：2016-02-16
申请号：US13166501
申请日：2011-06-22
申请人： Bin Duan , Lap Chan
发明人： Bin Duan , Lap Chan
IPC分类号： G06Q10/06 , H04W64/00
CPC分类号： G06Q10/0631 , H04W64/006
摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
摘要翻译：跟踪企业数据处理环境中的动作项目的系统和方法。该方法包括由客户端从服务器接收包括位置的动作项目。该方法还包括由客户端在与该动作项目相关的位置处执行登记。该方法还包括由客户端执行与该动作项目相关的退房。该方法还包括由客户端改变动作项目的状态。以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

8. 发明申请

US20140123068A1 Content Management Systems and Methods 有权
标题翻译：内容管理系统与方法
公开(公告)号：US20140123068A1
公开(公告)日：2014-05-01
申请号：US13661687
申请日：2012-10-26
申请人： Lap Chan
发明人： Lap Chan
IPC分类号： G06F3/048
CPC分类号： G06F3/04817 , G06F3/0482 , G06F3/0486 , G06F3/04886 , H04M1/72519
摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.
摘要翻译：描述了管理内容的示例系统和方法。在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

9. 发明授权

US07932152B2 Method of forming a gate stack structure 有权
标题翻译：形成栅极堆叠结构的方法
公开(公告)号：US07932152B2
公开(公告)日：2011-04-26
申请号：US12025789
申请日：2008-02-05
申请人： Will Wong , Lap Chan , Alan Lek
发明人： Will Wong , Lap Chan , Alan Lek
IPC分类号： H01L21/8234
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.
摘要翻译：一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。在衬底上形成第一厚度的第一材料的第一层。第一层的一部分在主区域上被去除以暴露衬底。该结构暴露于氧化介质。这形成例如基板的氧化物材料主区域的第二层。第二层具有第二厚度。另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。第三层具有第三厚度。

10. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

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