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1. 发明申请

US20090302421A1 Method and apparatus for creating a deep trench capacitor to improve device performance 审中-公开
标题翻译：用于产生深沟槽电容器以提高器件性能的方法和装置
公开(公告)号：US20090302421A1
公开(公告)日：2009-12-10
申请号：US12157211
申请日：2008-06-09
申请人： Charu Sardana , Bradley Jensen , Irfan Rahim , Jeffrey T. Watt
发明人： Charu Sardana , Bradley Jensen , Irfan Rahim , Jeffrey T. Watt
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/26586 , H01L21/28158 , H01L23/556 , H01L27/11 , H01L29/66537 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide.
摘要翻译：深沟槽电容器包括具有壁和地板的沟槽。深沟槽电容器还包括在墙壁和地板上的一层栅极氧化物。栅极多晶硅沉积在栅极氧化物上。

2. 发明申请

US20100090308A1 METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS 审中-公开
标题翻译：金属氧化物金属电容器与酒吧VIAS
公开(公告)号：US20100090308A1
公开(公告)日：2010-04-15
申请号：US12249901
申请日：2008-10-10
申请人： Charu Sardana , Albert Ratnakumar , Bradley Jensen , Jeffrey T. Watt
发明人： Charu Sardana , Albert Ratnakumar , Bradley Jensen , Jeffrey T. Watt
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.
摘要翻译：为集成电路提供带通孔的金属氧化物金属电容器。电容器可以形成在集成电路的互连层中。互连层中的堆叠的条形通孔和金属线可以连接以形成跨越多个互连层的导电垂直板。具有条形通孔的电容器可以通过将由堆叠的条形通孔和金属线形成的多个垂直板彼此平行地形成，交替相邻垂直平行板的极性而形成多个平行板电容器。平行板可以互连以在电容器中形成第一和第二端子。

3. 发明授权

US07321236B2 Apparatus and methods for programmable logic devices with improved performance characteristics 有权
标题翻译：具有改进的性能特征的可编程逻辑器件的装置和方法
公开(公告)号：US07321236B2
公开(公告)日：2008-01-22
申请号：US11672444
申请日：2007-02-07
申请人： Irfan Rahim , Jeffrey T. Watt
发明人： Irfan Rahim , Jeffrey T. Watt
IPC分类号： H03K17/16
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.
摘要翻译：公开了用于改善可编程逻辑器件（PLD）的性能的装置和方法。 PLD包括被配置为分别向传输晶体管的栅极和传输晶体管的主体提供一对电压的存储单元。

4. 发明授权

US08797790B1 Memory elements with soft error upset immunity 有权
标题翻译：内存元件具有软错误的不安定性
公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
申请人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
发明人： Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , William Bradley Vest
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化它的状态。晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

5. 发明授权

US08461869B1 Apparatus for configuring performance of field programmable gate arrays and associated methods 有权
标题翻译：用于配置现场可编程门阵列性能和相关方法的装置
公开(公告)号：US08461869B1
公开(公告)日：2013-06-11
申请号：US13214147
申请日：2011-08-19
申请人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
发明人： Irfan Rahim , Andy L. Lee , Bruce B. Pedersen , Jeffrey T. Watt , Mao Du , Richard G. Cliff
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17784
摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.
摘要翻译：一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号调节器所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

6. 发明申请

US20130127494A1 MEMORY ELEMENTS WITH RELAY DEVICES 有权
标题翻译：带继电器的记忆元件
公开(公告)号：US20130127494A1
公开(公告)日：2013-05-23
申请号：US13304226
申请日：2011-11-23
申请人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
发明人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
IPC分类号： H03K19/177 , G11C11/52
CPC分类号： G11C11/52 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , H01H1/20 , H01H59/0009 , H01L27/101 , H01L27/11
摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.
摘要翻译：提供具有存储元件的集成电路。集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分，中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。第一和第二部分中的装置可以接收相应的电源电压。在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

7. 发明申请

US20100321984A1 CONFIGURATION RANDOM ACCESS MEMORY 有权
标题翻译：配置随机存取存储器
公开(公告)号：US20100321984A1
公开(公告)日：2010-12-23
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： G11C11/24
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

8. 发明授权

US07463057B1 Integrated circuits with adjustable memory element power supplies 有权
标题翻译：具有可调存储元件电源的集成电路
公开(公告)号：US07463057B1
公开(公告)日：2008-12-09
申请号：US11394033
申请日：2006-03-29
申请人： Irfan Rahim , Jeffrey T. Watt , Yowjuang (Bill) Liu
发明人： Irfan Rahim , Jeffrey T. Watt , Yowjuang (Bill) Liu
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/17784
摘要： Integrated circuits such as programmable logic device integrated circuits are provided with adjustable configuration random-access-memory cell power supply circuitry. The adjustable configuration random-access-memory cell power supply circuitry powers configuration random-access-memory cells on an integrated circuit. During operation of the integrated circuit, the configuration random-access-memory cells provide static output signals that turn on and off associated pass transistors. The adjustable power supply circuitry can be configured to produce different power supply voltages on different portions of an integrated circuit. The different power supply voltages accommodate circuit design constraints while minimizing power consumption due to pass transistor leakage.
摘要翻译：诸如可编程逻辑器件集成电路的集成电路具有可调配置的随机存取存储单元电源电路。可调配置的随机存取存储单元电源电路为集成电路上的配置随机存取存储单元供电。在集成电路的操作期间，配置随机存取存储器单元提供导通和关断相关传输晶体管的静态输出信号。可调电源电路可以被配置为在集成电路的不同部分上产生不同的电源电压。不同的电源电压容纳电路设计约束，同时最小化由于传导晶体管泄漏引起的功耗。

9. 发明授权

US08289755B1 Volatile memory elements with soft error upset immunity 有权
标题翻译：易失性记忆元件，具有柔软的错误不耐受性
公开(公告)号：US08289755B1
公开(公告)日：2012-10-16
申请号：US12571346
申请日：2009-09-30
申请人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
发明人： Irfan Rahim , Jeffrey T. Watt , Andy L. Lee , Myron Wai Wong , William Bradley Vest
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
摘要翻译：提供了显示对软错误扰乱的抗扰度的内存元素。存储器元件可以具有交叉耦合的反相器。可以使用可编程施密特触发器来实现逆变器。存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。写使能晶体管可以桥接四个节点中的两个。存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。

10. 发明授权

US08089744B1 Apparatus and methods for electrostatic discharge circuitry with snap-back device 有权
标题翻译：具有快速恢复装置的静电放电电路的装置和方法
公开(公告)号：US08089744B1
公开(公告)日：2012-01-03
申请号：US11211060
申请日：2005-08-24
申请人： Irfan Rahim , Cheng Hsiung Huang , Yow-Juang Bill Liu , Jeffrey T. Watt , Hugh Sung-Ki O
发明人： Irfan Rahim , Cheng Hsiung Huang , Yow-Juang Bill Liu , Jeffrey T. Watt , Hugh Sung-Ki O
IPC分类号： H02H3/22
CPC分类号： H01L27/0277
摘要： An integrated circuit (IC) includes a multiple-finger transistor structure. The multiple-finger transistor structure includes one transistor configured as a ballasted device. The multiple-finger transistor structure further includes a second transistor configured as a trigger device for the ballasted device.
摘要翻译：集成电路（IC）包括多指晶体管结构。多指晶体管结构包括被配置为镇流器件的一个晶体管。多指晶体管结构还包括被配置为用于镇流器件的触发器件的第二晶体管。

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