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1. 发明申请

US20090302421A1 Method and apparatus for creating a deep trench capacitor to improve device performance 审中-公开
标题翻译：用于产生深沟槽电容器以提高器件性能的方法和装置
公开(公告)号：US20090302421A1
公开(公告)日：2009-12-10
申请号：US12157211
申请日：2008-06-09
申请人： Charu Sardana , Bradley Jensen , Irfan Rahim , Jeffrey T. Watt
发明人： Charu Sardana , Bradley Jensen , Irfan Rahim , Jeffrey T. Watt
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/26586 , H01L21/28158 , H01L23/556 , H01L27/11 , H01L29/66537 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide.
摘要翻译：深沟槽电容器包括具有壁和地板的沟槽。深沟槽电容器还包括在墙壁和地板上的一层栅极氧化物。栅极多晶硅沉积在栅极氧化物上。

2. 发明申请

US20100090308A1 METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS 审中-公开
标题翻译：金属氧化物金属电容器与酒吧VIAS
公开(公告)号：US20100090308A1
公开(公告)日：2010-04-15
申请号：US12249901
申请日：2008-10-10
申请人： Charu Sardana , Albert Ratnakumar , Bradley Jensen , Jeffrey T. Watt
发明人： Charu Sardana , Albert Ratnakumar , Bradley Jensen , Jeffrey T. Watt
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.
摘要翻译：为集成电路提供带通孔的金属氧化物金属电容器。电容器可以形成在集成电路的互连层中。互连层中的堆叠的条形通孔和金属线可以连接以形成跨越多个互连层的导电垂直板。具有条形通孔的电容器可以通过将由堆叠的条形通孔和金属线形成的多个垂直板彼此平行地形成，交替相邻垂直平行板的极性而形成多个平行板电容器。平行板可以互连以在电容器中形成第一和第二端子。

3. 发明授权

US09196749B1 Programmable device with a metal oxide semiconductor field effect transistor 有权
标题翻译：具有金属氧化物半导体场效应晶体管的可编程器件
公开(公告)号：US09196749B1
公开(公告)日：2015-11-24
申请号：US13341310
申请日：2011-12-30
申请人： Charu Sardana , Albert Ratnakumar , Qi Xiang , Bradley Jensen
发明人： Charu Sardana , Albert Ratnakumar , Qi Xiang , Bradley Jensen
IPC分类号： H01L29/66 , H01L29/788 , H01L27/112
CPC分类号： H01L27/112 , H01L27/11206 , H01L29/66 , H01L29/7881
摘要： A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.
摘要翻译：描述了由可编程衬底区域包围的具有金属氧化物半导体场效应晶体管（MOSFET）的可编程器件。 MOSFET具有由具有绝缘区域的沟道区域和设置在沟道区域上方的栅极分隔的源极和漏极区域。设置在衬底区域内的接合部控制可编程衬底区域。偏置连接点会耗尽衬底区域，从而将MOSFET的主体与次级阱隔离。当结点保持不偏差时，MOSFET的主体电耦合到次级阱。

4. 发明授权

US08609486B1 Methods for fabricating deep trench capacitors 有权
标题翻译：制造深沟槽电容器的方法
公开(公告)号：US08609486B1
公开(公告)日：2013-12-17
申请号：US13345630
申请日：2012-01-06
申请人： Peter Smeys , Charu Sardana
发明人： Peter Smeys , Charu Sardana
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： Integrated circuits with transistors and decoupling capacitor structures are provided. A decoupling capacitor structure may include multiple deep trench structures formed in a semiconductor substrate. The deep trench structures may each be lined with high-κ dielectric material. A conductive metal layer for use in controlling threshold voltages associated with n-channel or p-channel devices may be formed over the high-κ dielectric liner. Conductive material such as aluminum may be used to fill the remaining trench cavity. The high-κ dielectric liner may be simultaneously deposited into the deep trench structures and gate regions of the transistors. In one suitable arrangement, the deep trench structures and transistor metal gates for at least a selected type of transistors may be formed in parallel. In another suitable arrangement, the deep trench structures and the transistor metal gates may be formed in separate steps.
摘要翻译：提供了具有晶体管和去耦电容器结构的集成电路。去耦电容器结构可以包括形成在半导体衬底中的多个深沟槽结构。深沟槽结构可以各自用高kappa介电材料衬里。用于控制与n沟道或p沟道器件相关联的阈值电压的导电金属层可以形成在高卡介质衬垫上。可以使用诸如铝的导电材料来填充剩余的沟槽空腔。高卡介质衬垫可以同时沉积到晶体管的深沟槽结构和栅极区域中。在一种合适的布置中，用于至少一种选定类型的晶体管的深沟槽结构和晶体管金属栅极可以并联形成。在另一种合适的布置中，深沟槽结构和晶体管金属栅极可以分开形成。

5. 发明授权

US06265746B1 Highly resistive interconnects 失效
标题翻译：高电阻互连
公开(公告)号：US06265746B1
公开(公告)日：2001-07-24
申请号：US09228001
申请日：1999-01-08
申请人： Raminda U. Madurawe , Charu Sardana , Peter J. McElheny , Richard G. Smolen
发明人： Raminda U. Madurawe , Charu Sardana , Peter J. McElheny , Richard G. Smolen
IPC分类号： H01L2976
CPC分类号： H01L28/24 , H01L23/5226 , H01L23/5228 , H01L27/1112 , H01L27/1116 , H01L2924/0002 , H01L2924/00
摘要： Provided is a high resistance value vertically-integrated semiconductor interconnect with resistance in the 10 k&OHgr;-10 G&OHgr; range, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.
摘要翻译：提供了在10kOMEGA-10GOMEGA范围内具有电阻的高电阻值垂直集成半导体互连，以及以精确可控的方式与低电阻互连一起制造这种高电阻互连的工艺。此外，提供了一种具有用于上拉电阻的高电阻接触处理的SRAM单元。

6. 发明授权

US6127217A Method of forming highly resistive interconnects 有权
标题翻译：形成高电阻互连的方法
公开(公告)号：US6127217A
公开(公告)日：2000-10-03
申请号：US227992
申请日：1999-01-08
申请人： Raminda U. Madurawe , Charu Sardana , Peter J. McElheny , Richard G. Smolen
发明人： Raminda U. Madurawe , Charu Sardana , Peter J. McElheny , Richard G. Smolen
IPC分类号： H01L21/768 , H01L27/11 , H01L27/02 , H01L21/8242
CPC分类号： H01L21/76856 , H01L21/76841 , H01L21/76888 , H01L27/1112
摘要： Provided is a high resistance value vertically-integrated semiconductor interconnect, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.
摘要翻译：提供了一种高电阻值垂直集成的半导体互连，以及以精确可控的方式与低电阻互连一起制造这种高电阻互连的工艺。此外，提供了一种具有用于上拉电阻的高电阻接触处理的SRAM单元。

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