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1. 发明授权

US07463057B1 Integrated circuits with adjustable memory element power supplies 有权
标题翻译：具有可调存储元件电源的集成电路
公开(公告)号：US07463057B1
公开(公告)日：2008-12-09
申请号：US11394033
申请日：2006-03-29
申请人： Irfan Rahim , Jeffrey T. Watt , Yowjuang (Bill) Liu
发明人： Irfan Rahim , Jeffrey T. Watt , Yowjuang (Bill) Liu
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/17784
摘要： Integrated circuits such as programmable logic device integrated circuits are provided with adjustable configuration random-access-memory cell power supply circuitry. The adjustable configuration random-access-memory cell power supply circuitry powers configuration random-access-memory cells on an integrated circuit. During operation of the integrated circuit, the configuration random-access-memory cells provide static output signals that turn on and off associated pass transistors. The adjustable power supply circuitry can be configured to produce different power supply voltages on different portions of an integrated circuit. The different power supply voltages accommodate circuit design constraints while minimizing power consumption due to pass transistor leakage.
摘要翻译：诸如可编程逻辑器件集成电路的集成电路具有可调配置的随机存取存储单元电源电路。可调配置的随机存取存储单元电源电路为集成电路上的配置随机存取存储单元供电。在集成电路的操作期间，配置随机存取存储器单元提供导通和关断相关传输晶体管的静态输出信号。可调电源电路可以被配置为在集成电路的不同部分上产生不同的电源电压。不同的电源电压容纳电路设计约束，同时最小化由于传导晶体管泄漏引起的功耗。

2. 发明授权

US06905921B1 Advanced MOSFET design 失效
标题翻译：先进的MOSFET设计
公开(公告)号：US06905921B1
公开(公告)日：2005-06-14
申请号：US10800259
申请日：2004-03-11
申请人： Yowjuang (Bill) Liu , Francois Gregoire
发明人： Yowjuang (Bill) Liu , Francois Gregoire
IPC分类号： H01L21/265 , H01L21/336 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.
摘要翻译：本发明包括先进的MOSFET设计和制造方法，通过适当地解决与之相关的增加的泄漏问题，可以进一步提高IC封装密度。根据本发明的一个实施例的MOSFET包括在栅极的相对侧上的栅极，源极/漏极扩散区域以及与源极/漏极扩散区域相邻的源极/漏极延伸部分。 MOSFET还包括与源极/漏极延伸区域的至少一部分重叠的至少一个添加的拐角扩散区域，用于减少截止状态的漏电流。可以使用传统的CMOS IC制造工艺创建拐角扩散，同时对用于制造常规CMOS IC的离子注入掩模进行一些修改。

3. 发明授权

US06777721B1 SCR device for ESD protection 有权
标题翻译：用于ESD保护的SCR器件
公开(公告)号：US06777721B1
公开(公告)日：2004-08-17
申请号：US10298104
申请日：2002-11-14
申请人： Cheng Huang , Yowjuang (Bill) Liu
发明人： Cheng Huang , Yowjuang (Bill) Liu
IPC分类号： H01C2974
CPC分类号： H01L27/0262 , H01L29/87
摘要： The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.
摘要翻译：本发明提供了用于保护集成电路（IC）免受ESD损坏的新型ESD结构以及在半导体衬底上制造ESD结构的方法。本发明的ESD结构具有较低的触发电压和较低的电容，并且比现有技术的ESD结构具有更小的衬底面积。低触发电压由小N + P二极管或P + N二极管提供，其具有比N +（或P +）源极/漏极区域之间的PN结低得多的击穿电压的PN结，以及 P井（或N井）。本发明的ESD器件中的所有扩散区域可以通过用于制造IC中的MOS器件的常规工艺步骤形成，除了制造IC所需的那些之外，不需要额外的掩模步骤。

4. 发明授权

US07821050B1 CRAM transistors with high immunity to soft error 有权
标题翻译： CRAM晶体管具有较高的抗软性误差
公开(公告)号：US07821050B1
公开(公告)日：2010-10-26
申请号：US11497017
申请日：2006-07-31
申请人： Yowjuang (Bill) Liu , Cheng-Hsiung Huang , Chih-Ching Shih
发明人： Yowjuang (Bill) Liu , Cheng-Hsiung Huang , Chih-Ching Shih
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/118 , G11C5/005 , G11C11/4125 , H01L27/11 , H01L27/1104 , H01L29/4983 , H01L29/66659 , Y10S257/903
摘要： A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.
摘要翻译：制造在半导体衬底上的晶体管包括衬底中的源极和漏极; 基板上的栅极，栅极通过栅极电介质与基板绝缘; 覆盖栅极和栅极电介质的两侧的阻挡层; 覆盖阻挡层的高k材料的间隔物; 以及覆盖高k材料的间隔物的氮化物间隔物。高k材料的间隔物显着增加了晶体管的节点电容，从而降低了晶体管的软错误率。

5. 发明授权

US07195958B1 Methods of fabricating ESD protection structures 失效
标题翻译：制造ESD保护结构的方法
公开(公告)号：US07195958B1
公开(公告)日：2007-03-27
申请号：US10882874
申请日：2004-06-30
申请人： Cheng Huang , Yowjuang (Bill) Liu
发明人： Cheng Huang , Yowjuang (Bill) Liu
IPC分类号： H01L21/332
CPC分类号： H01L27/0262 , H01L29/87
摘要： The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.
摘要翻译：本发明提供了用于保护集成电路（IC）免受ESD损坏的新型ESD结构以及在半导体衬底上制造ESD结构的方法。本发明的ESD结构具有较低的触发电压和较低的电容，并且比现有技术的ESD结构具有更小的衬底面积。低触发电压由小的N + P / P二极管或具有比其间的PN结低得多的击穿电压的PN结的P + N +（或P +）源/漏区和P阱（或N阱）。本发明的ESD器件中的所有扩散区域可以通过用于制造IC中的MOS器件的常规工艺步骤形成，除了制造IC所需的那些之外，不需要额外的掩模步骤。

6. 发明授权

US08232602B2 ESD protection device for high performance IC 有权
标题翻译： ESD保护器件，用于高性能IC
公开(公告)号：US08232602B2
公开(公告)日：2012-07-31
申请号：US11710651
申请日：2007-02-23
申请人： Yowjuang (Bill) Liu , Cheng Huang
发明人： Yowjuang (Bill) Liu , Cheng Huang
IPC分类号： H01L23/62
CPC分类号： H01L27/027 , H01L21/823418 , H01L27/0266
摘要： The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.
摘要翻译：本发明包括用于ESD保护的电路结构和制作电路结构的方法。电路结构可用于ESD保护电路中，以保护集成电路中的某些器件，并且除了用于制造集成电路中的ESD保护器件的处理步骤之外，还可以不需要额外的处理步骤来制造电路结构。

7. 发明授权

US07514758B2 Dual-oxide transistors for the improvement of reliability and off-state leakage 有权
标题翻译：双氧化物晶体管用于提高可靠性和截止状态的泄漏
公开(公告)号：US07514758B2
公开(公告)日：2009-04-07
申请号：US11149049
申请日：2005-06-08
申请人： Peter John McElheny , Yowjuang (Bill) Liu
发明人： Peter John McElheny , Yowjuang (Bill) Liu
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L21/28123 , H01L21/823864 , H01L29/42368 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/981
摘要： The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.
摘要翻译：本发明提供一种具有低漏电流的晶体管和在半导体衬底上制造晶体管的方法。晶体管在栅极下方具有栅极和不均匀的栅极氧化物。

8. 发明申请

US20070243492A1 Double exposure photolithographic process 审中-公开
标题翻译：双曝光光刻工艺
公开(公告)号：US20070243492A1
公开(公告)日：2007-10-18
申请号：US11710650
申请日：2007-02-23
申请人： Peter J. McElheny , Yowjuang (Bill) Liu
发明人： Peter J. McElheny , Yowjuang (Bill) Liu
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , G03F7/70425 , G03F7/70466
摘要： A first high resolution pattern is defined in a first layer of photoresist on a work surface and portions of the first layer are removed to expose the pattern on the work surface. The exposed portions of the work surface and the remaining portions of the first layer are then covered by a second layer of photoresist. A second lower resolution pattern is then defined in the second layer and portions of the second layer are removed to expose on the work surface a third pattern that is a subset of the first pattern. Standard (non-custom) masks may be used to define the first pattern while custom but lower resolution masks are used to define the second pattern.
摘要翻译：在工作表面上的第一层光致抗蚀剂中限定第一高分辨率图案，并且去除第一层的部分以露出工作表面上的图案。工作表面的暴露部分和第一层的剩余部分然后被第二层光致抗蚀剂覆盖。然后在第二层中限定第二较低分辨率图案，并且去除第二层的部分以在工作表面上露出作为第一图案的子集的第三图案。可以使用标准（非定制）掩模来定义第一图案，而定制但较低分辨率的掩模用于定义第二图案。

9. 发明授权

US08159044B1 Density transition zones for integrated circuits 有权
标题翻译：集成电路密度过渡区
公开(公告)号：US08159044B1
公开(公告)日：2012-04-17
申请号：US12623161
申请日：2009-11-20
申请人： Shuxian Chen , Fangyun Richter , Bradley Jensen , Yowjuang (Bill) Liu
发明人： Shuxian Chen , Fangyun Richter , Bradley Jensen , Yowjuang (Bill) Liu
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L23/522 , H01L27/0207 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.
摘要翻译：集成电路设置有螺旋电感器和围绕螺旋电感器的过渡区域。过渡区域可以具有基本上八边形或八边形的几何形状。过渡区域中的金属层可以具有基本上八边形并且以行和列排列的金属填充物。如果需要，方形或矩形金属填充物与基本上八角形的金属填充物平铺。金属层也可以包含一半或四分之八角金属填充物。过渡区中的衬底可以具有由浅沟槽隔离区隔开的八边形衬底区域。衬底上方的多晶硅层可以具有直接在衬底中的浅沟槽区域上方的多晶硅的正方形区域。这种布置可以在具有某些几何形状的过渡区域中提供更均匀的密度。

10. 发明授权

US07471493B1 Fast and compact SCR ESD protection device for high-speed pins 失效
标题翻译：用于高速引脚的快速紧凑的SCR ESD保护器件
公开(公告)号：US07471493B1
公开(公告)日：2008-12-30
申请号：US11365070
申请日：2006-02-28
申请人： Cheng-Hsiung Huang , Chih-Ching Shih , Hugh Sung-Ki O , Yowjuang (Bill) Liu
发明人： Cheng-Hsiung Huang , Chih-Ching Shih , Hugh Sung-Ki O , Yowjuang (Bill) Liu
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0262 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A pair of SCR devices connected in antiparallel between first and second nodes. Each SCR device comprises an NPN and a PNP bipolar transistor. Reverse-biased Zener diodes are used for triggering the NPN bipolar transistor in each SCR device when it breaks down in an ESD event. Advantageously, additional Zener diodes are provided for pre-charging the PNP transistor of each SCR device at the same time, thereby reducing the delay time for turning on the PNP bipolar transistor. In addition, the breakdown current of the Zener diodes is preferably maximized by reducing the P-well and N-well resistance of the SCRs. This is achieved by connecting external resistances between the base of each bipolar transistor and the node to which the emitter of the transistor is connected.
摘要翻译：在第一和第二节点之间反并联连接的一对SCR设备。每个SCR器件包括NPN和PNP双极晶体管。反向偏置齐纳二极管用于在ESD事件中发生故障时触发每个SCR器件中的NPN双极晶体管。有利地，提供了额外的齐纳二极管，用于同时为每个SCR器件的PNP晶体管预充电，从而减少了导通PNP双极晶体管的延迟时间。此外，通过降低SCR的P阱和N阱电阻，优选使齐纳二极管的击穿电流最大化。这是通过连接每个双极晶体管的基极与晶体管的发射极连接的节点之间的外部电阻来实现的。

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