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1. 发明申请

US20050060624A1 Programmable hysteresis for boundary-scan testing 有权
标题翻译：边界扫描测试的可编程滞后
公开(公告)号：US20050060624A1
公开(公告)日：2005-03-17
申请号：US10666770
申请日：2003-09-17
申请人： Charles Moore , Xiaoyang Zhang , Jeffrey Rearick
发明人： Charles Moore , Xiaoyang Zhang , Jeffrey Rearick
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/2815 , G01R31/31855 , G01R31/318572
摘要： Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.
摘要翻译：公开了一种用于在板互连测试期间捕获信号的边界扫描测试接收器。测试接收机具有比较器，其具有第一输入以在电路板互连测试期间接收信号，以及第二输入以接收参考电压。可编程迟滞电路耦合到至少一个比较器的输入端。可编程迟滞电路可以被配置为对滞后电压和/或滞后延迟进行编程，这两者都有助于防止比较器积分信号噪声。

2. 发明申请

US20130159376A1 SYSTEMS AND METHODS FOR A COMPUTING RESOURCE BROKER AGENT 审中-公开
标题翻译：计算资源经纪人代理的系统和方法
公开(公告)号：US20130159376A1
公开(公告)日：2013-06-20
申请号：US13715835
申请日：2012-12-14
申请人： Charles Moore
发明人： Charles Moore
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , G06F9/5072 , H04L67/2809
摘要： A resource broker agent may be configured to monitor computing resources available on a computing device. The resource broker agent may be further configured to request additional computing resources in response to detecting a request to perform a computing task that cannot be adequately performed with the computing resources currently available on the computing device. The additional computing resources may be requested from one or more remote resource providers via a network. The additional computing resources may comprise remote execution of portions of the computing task. The resource broker agent may be further configured to perform the requested computing task by use of a virtualized computing environment of the computing device.
摘要翻译：资源代理代理可以被配置为监视计算设备上可用的计算资源。可以进一步配置资源代理代理以响应于检测到执行计算任务的请求而无法用计算设备上当前可用的计算资源进行适当的执行来请求额外的计算资源。可以经由网络从一个或多个远程资源提供者请求附加的计算资源。附加的计算资源可以包括计算任务的部分的远程执行。资源代理代理可以被进一步配置成通过使用计算设备的虚拟化计算环境来执行所请求的计算任务。

3. 发明授权

US08097709B2 Macrolactam compounds 有权
标题翻译：丁内酰胺化合物
公开(公告)号：US08097709B2
公开(公告)日：2012-01-17
申请号：US12196714
申请日：2008-08-22
申请人： Aaron Peoples , Qibo Zhang , Charles Moore , Lucy Ling , Mithra Rothfeder , Kim Lewis
发明人： Aaron Peoples , Qibo Zhang , Charles Moore , Lucy Ling , Mithra Rothfeder , Kim Lewis
IPC分类号： C07H17/02 , A01N43/04 , A61K31/70
CPC分类号： C07D309/14
摘要： The invention relates generally to novel macrolactams and their analogs, to processes for the preparation of these novel macrolactams, to pharmaceutical compositions comprising the novel macrolactams; and to methods of using the novel macrolactams to treat or inhibit various disorders.
摘要翻译：本发明一般涉及新颖的大环内酰胺及其类似物，用于制备这些新型的大内酰胺的方法，用于包含新型大环内酯的药物组合物; 以及使用新型大环内酰胺来治疗或抑制各种疾病的方法。

4. 发明申请

US20090147091A1 Method, apparatus and system for image stabilization using a single pixel array 有权
标题翻译：使用单个像素阵列进行图像稳定的方法，装置和系统
公开(公告)号：US20090147091A1
公开(公告)日：2009-06-11
申请号：US11987869
申请日：2007-12-05
申请人： Charles Myers , Michael J. Brosnan , Charles Moore , Richard A. Baumgartner , Christopher Silsby , Brian J. Misek
发明人： Charles Myers , Michael J. Brosnan , Charles Moore , Richard A. Baumgartner , Christopher Silsby , Brian J. Misek
IPC分类号： H04N5/228
CPC分类号： H04N5/23248 , H04N5/23254 , H04N5/2327
摘要： An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.
摘要翻译：公开了一种成像像素阵列及其相关联的方法和系统，其中阵列包含每个具有第一光转换装置的第一像素，以及每个具有第一光转换装置和第二光转换装置的第二像素。第一光转换装置被配置为在第一积分周期期间获取图像。第二光转换装置被配置为在第一积分周期期间获取多个图像。电路使用多个图像信号，并且在第一积分周期的一部分期间从其确定阵列与图像之间的相对运动，并且提供表示用于图像稳定的运动的信号。

5. 发明申请

US20070226457A1 Computer system with increased operating efficiency 有权
标题翻译：提高运行效率的计算机系统
公开(公告)号：US20070226457A1
公开(公告)日：2007-09-27
申请号：US11653187
申请日：2007-01-12
申请人： Charles Moore , Jeffrey Fox , John Rible
发明人： Charles Moore , Jeffrey Fox , John Rible
IPC分类号： G06F15/00
CPC分类号： G06F1/32
摘要： A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.
摘要翻译：一种微处理器系统，其中处理器阵列通过使用工作模式功能更有效地进行通信。当前不执行代码的处理器保持处于非活动状态，但是在相邻处理器发送任务之前，该状态保持不活动状态。处理器也可以编程为暂时挂起任务以检查传入的任务或消息。

6. 发明申请

US20060208805A1 Linear phase-locked loop with dual tuning elements 有权
标题翻译：具有双调谐元件的线性锁相环
公开(公告)号：US20060208805A1
公开(公告)日：2006-09-21
申请号：US11084376
申请日：2005-03-18
申请人： Brian Galloway , Gunter Steinbach , Charles Moore
发明人： Brian Galloway , Gunter Steinbach , Charles Moore
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A linear PLL includes a VCO with first and second tuning elements. The first tuning element is adjusted in proportion to the phase error between an input signal and a VCO signal and the second tuning element is adjusted by an integral function of the phase error. By configuring the VCO with separate tuning elements that are separately adjusted in proportion to the phase error and by an integral function of the phase error, the 3 dB bandwidth frequency of the linear PLL depends primarily on the phase detector gain and the VCO gain that is contributed from the proportional adjustment. A linear PLL with separate proportional and integral tuning elements can be designed to exhibit a relatively constant gain over a relatively large frequency range.
摘要翻译：线性PLL包括具有第一和第二调谐元件的VCO。第一调谐元件与输入信号和VCO信号之间的相位误差成比例地调整，并且通过相位误差的积分函数来调整第二调谐元件。通过使用单独的调谐元件配置VCO，该调谐元件与相位误差成比例地分别调整，并通过相位误差的积分函数，线性PLL的3 dB带宽频率主要取决于相位检测器增益和VCO增益由比例调整贡献。具有分开的比例和积分调谐元件的线性PLL可以设计成在相对大的频率范围内呈现相对恒定的增益。

7. 发明申请

US20050121766A1 Integrated circuit and method of manufacturing an integrated circuit and package 审中-公开
标题翻译：集成电路和制造集成电路和封装的方法
公开(公告)号：US20050121766A1
公开(公告)日：2005-06-09
申请号：US11031774
申请日：2005-01-07
申请人： Nurwati Devnani , James Barnes , Charles Moore , Benny Lai
发明人： Nurwati Devnani , James Barnes , Charles Moore , Benny Lai
IPC分类号： H01L21/44 , H01L23/498 , H01L23/52 , H01L23/64
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/642 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
摘要： A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.
摘要翻译：封装的IC包括具有相对于彼此定位的信号和信号补偿迹线的IC管芯，以使匹配阻抗最大化边缘耦合。信号和信号补码迹线电连接到IC芯片的传输或接收通道。使用宽边耦合迹线配置减轻了IC封装中的布线拥塞，并允许IC在给定的表面区域内容纳比现有技术中可能的更多数量的通道。

8. 发明授权

US5999028A Differential circuits with adjustable propagation timing 失效
标题翻译：差分电路具有可调传播时间
公开(公告)号：US5999028A
公开(公告)日：1999-12-07
申请号：US995886
申请日：1997-12-22
申请人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
发明人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
IPC分类号： H03K19/0944 , H03F3/45 , H03K5/24 , H03K5/12 , G06G7/10
CPC分类号： H03F3/45771 , H03F3/45479 , H03K5/2481 , H03F2203/45624 , H03F2203/45646 , H03F2203/45702
摘要： Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.
摘要翻译：描述了一种用于在两个基本上对称构建的电流路径处接收差分输入信号并用于从其提供输出信号的电路。至少一个电流路径包括用于将输入信号的定时信息调整为输出信号的定时信息的装置。可以通过修改相应电流路径中的电压电平来实现调整，直到输出信号的定时信息至少基本上表示输入信号的定时信息，例如，通过修改各个电流路径中的阻抗或电流。通过用已知的定时信息应用定义的输入信号来执行定时信息的调整，将所得到的输出信号的定时信息与输入信号的定时信息进行比较，并修改至少一个电压电平直到输出和输入信号的定时信息至少基本匹配的电流路径。

9. 发明授权

US08499676B1 Coupler system for attaching blank adaptor and the like to a flash hider 有权
标题翻译：用于将空白适配器等附接到闪光灯的耦合器系统
公开(公告)号：US08499676B1
公开(公告)日：2013-08-06
申请号：US13211811
申请日：2011-08-17
申请人： Charles Moore , Thomas Mooty
发明人： Charles Moore , Thomas Mooty
IPC分类号： F41A21/32
CPC分类号： F41A21/325 , F41A17/44 , F41A21/26 , F41A21/30
摘要： A coupling system attaches a device such as a blank adaptor or a sound suppressor to the flash hider of a firearm. The device is slid over the flash hider until a set of flat surfaces on it are aligned with a set of holes in the device. Camming latches are held in the holes in the device. The collar carried by the device is then threadably advanced to a locking position with respect to the device where it presses the camming latches into secure engagement with the flat surfaces on the flash hider. Unthreading the collar to the unlocked position allows the camming latches to be moved radially when the device is to be removed or rotated. A spring lock prevents the collar from rotating during use, particularly during firing of the firearm but may be released to rotate the collar between locked and unlocked positions.
摘要翻译：耦合系统将诸如空白适配器或声音抑制器的装置附接到枪支的闪光灯。该装置滑过闪光灯，直到其上的一组平坦表面与装置中的一组孔对准。凸轮锁扣保持在设备的孔中。然后将装置承载的衣领螺纹地推进到相对于装置的锁定位置，在那里它将凸轮闩锁按压到与闪光灯的平坦表面牢固接合。将套环拧开到未锁定位置可以使装置在拆卸或旋转时使凸轮闩锁径向移动。弹簧锁防止套环在使用期间旋转，特别是在枪械射击期间可以旋转，但可以释放以在锁定位置和解锁位置之间旋转套环。

10. 发明申请

US20080072021A1 Floating point exception handling in a risc microprocessor architecture 审中-公开
公开(公告)号：US20080072021A1
公开(公告)日：2008-03-20
申请号：US11981453
申请日：2007-10-31
申请人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
发明人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
IPC分类号： G06F9/302
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

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