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1. 发明授权

US5999028A Differential circuits with adjustable propagation timing 失效
标题翻译：差分电路具有可调传播时间
公开(公告)号：US5999028A
公开(公告)日：1999-12-07
申请号：US995886
申请日：1997-12-22
申请人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
发明人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
IPC分类号： H03K19/0944 , H03F3/45 , H03K5/24 , H03K5/12 , G06G7/10
CPC分类号： H03F3/45771 , H03F3/45479 , H03K5/2481 , H03F2203/45624 , H03F2203/45646 , H03F2203/45702
摘要： Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.
摘要翻译：描述了一种用于在两个基本上对称构建的电流路径处接收差分输入信号并用于从其提供输出信号的电路。至少一个电流路径包括用于将输入信号的定时信息调整为输出信号的定时信息的装置。可以通过修改相应电流路径中的电压电平来实现调整，直到输出信号的定时信息至少基本上表示输入信号的定时信息，例如，通过修改各个电流路径中的阻抗或电流。通过用已知的定时信息应用定义的输入信号来执行定时信息的调整，将所得到的输出信号的定时信息与输入信号的定时信息进行比较，并修改至少一个电压电平直到输出和输入信号的定时信息至少基本匹配的电流路径。

2. 发明申请

US20070005285A1 METHOD AND APPARATUS FOR CALIBRATING DELAY LINES 失效
标题翻译：用于校准延迟线的方法和装置
公开(公告)号：US20070005285A1
公开(公告)日：2007-01-04
申请号：US11170207
申请日：2005-06-29
申请人： Ronnie Owens , Theodore Rossin , Larry Metz
发明人： Ronnie Owens , Theodore Rossin , Larry Metz
IPC分类号： G01R27/28
CPC分类号： G01R31/31725 , G01R31/3191 , H03K2005/0011
摘要： A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.
摘要翻译：用于产生测试图形波形的延迟线（DL）电路具有在校准期间使用的脉冲发生电路，以在接收到信号边缘时产生脉冲信号。 DL电路的延迟线接收脉冲信号并将脉冲信号延迟选定的时间延迟。 DL电路的反馈环路将从延迟线输出的延迟脉冲信号馈送回脉冲发生电路的输入端。在脉冲发生电路的输入处接收反馈脉冲信号的边沿使脉冲发生电路产生另一个脉冲信号。从延迟线输出的延迟脉冲信号可以输入到产生基于延迟脉冲信号的振荡周期的计数器值的计数器。

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