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1. 发明授权

US08910208B2 Interactive video system 有权
标题翻译：互动视频系统
公开(公告)号：US08910208B2
公开(公告)日：2014-12-09
申请号：US12962529
申请日：2010-12-07
申请人： Anthony Hartman , George Shaw
发明人： Anthony Hartman , George Shaw
IPC分类号： H04N7/14 , H04N5/445 , H04N7/173 , H04N21/475 , H04N7/15 , H04N21/4788 , H04N21/422 , H04N21/4223 , H04N21/443
CPC分类号： H04N21/4788 , H04N7/15 , H04N21/42203 , H04N21/4223 , H04N21/4438 , H04N21/4755
摘要： An interactive video system is provided that is capable of combining streaming televised events with video conferencing technology to create a social television experience. A first user is able to connect via a webcam and microphone to a server that combines the webcam video and sound from the microphone with a streaming video that could be a televised event. The combined webcam video, microphone sound, and streaming video is then broadcast to the first user and other users such that the users are capable of viewing the streaming video with the live conferencing video and sound from the first user. This procedure may be repeated such that a plurality of users may video conference live on top of the streaming video.
摘要翻译：提供了一种交互式视频系统，其能够将流媒体电视事件与视频会议技术相结合，以创建社交电视体验。第一个用户能够通过网络摄像头和麦克风连接到将麦克风的网络摄像头视频和声音与可以是电视转播事件的流式视频相结合的服务器。然后将组合的网络摄像头视频，麦克风声音和流视频广播到第一用户和其他用户，使得用户能够使用来自第一用户的现场会议视频和声音来观看流式视频。可以重复该过程，使得多个用户可以在流式视频的顶部上进行视频会议。

2. 发明申请

US20140243647A1 APPARATUSES AND METHODS FOR NEUROLOGICAL STATUS EVALUATION USING ELECTROMAGNETIC SIGNALS 有权
标题翻译：使用电磁信号进行神经病学状态评估的装置和方法
公开(公告)号：US20140243647A1
公开(公告)日：2014-08-28
申请号：US13977689
申请日：2011-12-30
申请人： Joseph Floyd Clark , Matthew L. Flaherty , George Shaw , Opeolu Adeoye
发明人： Joseph Floyd Clark , Matthew L. Flaherty , George Shaw , Opeolu Adeoye
IPC分类号： A61B5/00 , A61B5/02
CPC分类号： A61B5/04008 , A61B5/0042 , A61B5/0075 , A61B5/02042 , A61B5/04001 , A61B5/4064 , A61B5/4094 , A61B5/4878 , A61B5/6803 , A61B5/7225 , A61B5/7257 , A61B5/7282 , A61B5/742 , A61B5/746 , A61B2562/0223 , A61B2576/026
摘要： In one embodiment, a neurological status evaluation apparatus includes a signal generator configured to generate an electromagnetic signal at one or more frequencies, a transmitting antenna coupled to the signal generator and configure to transmit the electromagnetic signal, and a receiving antenna positioned proximate to the transmitting antenna such that an evaluation space is defined between the transmitting antenna and the receiving antenna. The biological tissue under evaluation does not contact the transmitting antenna or the receiving antenna. The receiving antenna receives a modulated electromagnetic signal after propagating through the biological tissue under evaluation. The neurological status evaluation apparatus further includes a spectrum analyzer coupled to the receiving antenna, wherein the spectrum analyzer receives and samples the modulated electromagnetic signal. A computing device is coupled to the spectrum analyzer, calculates an evaluation, and provides a neurological status indicator of the biological tissue under evaluation based on the evaluation parameter.
摘要翻译：在一个实施例中，神经状态评估装置包括被配置为产生一个或多个频率的电磁信号的信号发生器，耦合到信号发生器并被配置为传送电磁信号的发射天线以及靠近发射天线，使得在发射天线和接收天线之间定义评估空间。所评估的生物组织不接触发射天线或接收天线。接收天线在评估后通过生物组织传播后接收调制电磁信号。神经状态评估装置还包括耦合到接收天线的频谱分析仪，其中频谱分析仪接收并采样调制的电磁信号。计算设备耦合到频谱分析仪，计算评估，并根据评估参数提供正在评估的生物组织的神经状态指标。

3. 发明申请

US20130222599A1 METHOD AND SYSTEM FOR FULL PATH ANALYSIS 审中-公开
标题翻译：全路径分析方法与系统
公开(公告)号：US20130222599A1
公开(公告)日：2013-08-29
申请号：US13603832
申请日：2012-09-05
申请人： George SHAW
发明人： George SHAW
IPC分类号： G06K9/60
CPC分类号： G06K9/60 , G06K9/00771
摘要： A space is modeled using images from a set of cameras in the space. An easy to use tool is provided that allows users to identify a reference location in an image and a corresponding reference location on a floor plan of the space. Based on these correspondences, a model is generated that can map a point in a camera's view to a point on the floor plan, or vice-versa. Subjects moving through the space are identified and tracked using the model and attributes associated with a subject. In a specific implementation, the attributes include velocity, color, size, and position. In a specific implementation, the space is a retail store and the subjects are customers browsing through the retail store.
摘要翻译：空间用空间中的一组相机的图像建模。提供了易于使用的工具，其允许用户在空间的平面图上识别图像中的参考位置和对应的参考位置。基于这些对应关系，生成可以将相机视图中的点映射到平面图上的点的模型，反之亦然。使用与主题相关联的模型和属性来识别和跟踪移动通过空间的对象。在具体实现中，属性包括速度，颜色，大小和位置。在具体实施中，空间是零售商店，主题是浏览零售商店的顾客。

4. 发明申请

US20120034254A1 ANTIGENIC CLOAKING AND ITS USE 审中-公开
标题翻译：抗原克隆及其使用
公开(公告)号：US20120034254A1
公开(公告)日：2012-02-09
申请号：US12866723
申请日：2009-02-06
申请人： Peter D. Kwong , Gary J. Nabel , George Shaw , William Schief , Zhi-yong Yang , Tongqing Zhou , Lei Chen , Young Do Kwon
发明人： Peter D. Kwong , Gary J. Nabel , George Shaw , William Schief , Zhi-yong Yang , Tongqing Zhou , Lei Chen , Young Do Kwon
IPC分类号： A61K39/21 , C07K14/195 , C07K14/37 , C07K14/005 , A61P31/18 , A61K39/00 , C07H21/00 , G01N33/566 , A61P37/04 , C07K14/16 , C07H21/04
CPC分类号： C07K14/005 , A61K39/12 , A61K39/21 , A61K2039/545 , A61K2039/55566 , C12N2740/15022 , C12N2740/16122 , C12N2740/16134 , G16B15/00 , G16B20/00
摘要： Disclosed are antigens that include a target epitope that is defined by atomic coordinates of those amino acids of the antigen that contact an antibody of interest that specifically binds the antigen. The disclosed antigens have between about 10% and about 90% of surface exposed amino acid residues located exterior of the target epitope substituted as compared to a wild-type antigen and less than about 10% of the non-surface exposed amino acid residues substituted as compared to a wild-type antigen. Also disclosed are nucleic acids encoding these antigens and methods of producing these antigens. Methods for generating an immune response in a subject are also disclosed. In some embodiments, the method is a method for treating or preventing a human immunodeficiency type 1 (HIV-1) infection in a subject.
摘要翻译：公开的是包含由与抗原特异性结合的目的抗体接触的抗原的那些氨基酸的原子坐标定义的靶表位的抗原。与野生型抗原相比，所公开的抗原具有位于目标表位外部取代的表面暴露的氨基酸残基的约10％至约90％，并且小于约10％的非表面暴露的氨基酸残基被取代为与野生型抗原相比。还公开了编码这些抗原的核酸和产生这些抗原的方法。还公开了在受试者中产生免疫应答的方法。在一些实施方案中，该方法是用于治疗或预防受试者中的人类免疫缺陷1型（HIV-1）感染的方法。

5. 发明申请

US20080091920A1 Transferring data between registers in a RISC microprocessor architecture 审中-公开
公开(公告)号：US20080091920A1
公开(公告)日：2008-04-17
申请号：US11981237
申请日：2007-10-31
申请人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
发明人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
IPC分类号： G06F9/00 , G06F9/30
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

6. 发明申请

US20080077911A1 Using breakpoints for debugging in a RISC microprocessor architecture 审中-公开
公开(公告)号：US20080077911A1
公开(公告)日：2008-03-27
申请号：US11981278
申请日：2007-10-31
申请人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
发明人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
IPC分类号： G06F9/44
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

7. 发明申请

US20070271442A1 Detecting the boundaries of memory in a RISC microprocessor architecture 审中-公开
公开(公告)号：US20070271442A1
公开(公告)日：2007-11-22
申请号：US11881284
申请日：2007-07-26
申请人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
发明人： George Shaw , Martin McClurg , Bradley Jensen , Russell Fish , Charles Moore
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/30014 , G06F9/3005 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3861 , G06F9/3877 , G06F9/3879 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/126
摘要： A microprocessor executes at 100 native MIPS peak performance with a 100-MHz internal clock frequency. Central processing unit (CPU) instruction sets are hardwired, allowing most instructions to execute in a single cycle. A “flow-through” design allows the next instruction to start before the prior instruction completes, thus increasing performance. A microprocessing unit (MPU) contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top elements, are cached on chip, and when required, automatically spill to and refill from external memory. The stacks minimize the data movement and also minimize memory access during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register and 41 locally addressed registers for I/O, control, configuration, and status. The CPU contains both a high-performance, zero-operand, dual-stack architecture MPU, and an input-output processor (IOP) that executes instructions to transfer data, count events, measure time, and perform other timing-dependent functions. A zero-operand stack architecture eliminates operand bits. Stacks also minimize register saves and loads within and across procedures, thus allowing shorter instruction sequences and faster-running code. Instructions are simple to decode and execute, allowing the MPU and IOP to issue and complete instructions in a single clock cycle—each at 100 native MIPS peak execution. Using 8-bit opcodes, the CPU obtains up to four instructions from memory each time an instruction fetch or pre-fetch is performed. These instructions can be repeated without rereading them from memory. This maintains high performance when connected directly to DRAM, without a cache.

8. 发明申请

US20050286552A1 Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules 有权
标题翻译：流式数据帧的高效分割和混合，用于通过多个处理模块进行处理
公开(公告)号：US20050286552A1
公开(公告)日：2005-12-29
申请号：US11204683
申请日：2005-08-16
申请人： Rafael Lisitsa , George Shaw , Dale Sather , Bryan Woodruff
发明人： Rafael Lisitsa , George Shaw , Dale Sather , Bryan Woodruff
IPC分类号： H04J3/16
CPC分类号： G06F15/8053
摘要： Streaming data is processed through one or more pipes of connected modules including mixers and/or splitters. The data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other transform modules. Nesting trees and pipe control tables represent the structure of the pipes. A frame allocator is assigned to a particular module in a pipe. Rather than issuing a control transaction to all modules when any one of them completes an operation upon its source data, a control manager requests a module to begin its operation only when all of its input subframes have become available. Frame control tables record when any module has completed an operation, and a pipe control table lists which modules provide data to which other modules.
摘要翻译：流数据通过一个或多个连接的模块管道进行处理，包括混合器和/或分离器。该数据在具有与分离器，混合器和其他变换模块中的不同分配器相关联的虚拟子帧的复合物理分配帧中承载。嵌套树木和管道控制表表示管道的结构。帧分配器被分配给管道中的特定模块。控制管理器当其任何一个完成其源数据上的操作时，不会向所有模块发出控制事务，而是只有当所有模块的所有输入子帧都可用时才要求模块开始操作。任何模块完成操作时，帧控制表记录，管道控制表列出哪些模块向其他模块提供数据。

9. 发明申请

US20050221301A1 Reference clones and sequences for non-subtype B isolates of human immunodeficiency virus type 1 失效
公开(公告)号：US20050221301A1
公开(公告)日：2005-10-06
申请号：US11135597
申请日：2005-05-23
申请人： Beatrice Hahn , George Shaw , Feng Gao
发明人： Beatrice Hahn , George Shaw , Feng Gao
IPC分类号： A01N63/00 , A01N63/04 , A61K8/22 , A61K8/60 , A61K8/66 , A61Q5/00 , A61Q11/00 , A61Q17/00 , A61Q19/00 , C07H21/02 , C07K14/16 , C09D5/02 , C09D5/14 , C11D3/00 , C11D3/20 , C11D3/386 , C11D3/48 , C12Q1/68 , C12Q1/70
CPC分类号： C07K14/005 , A01N63/00 , A01N63/04 , A61K8/22 , A61K8/602 , A61K8/66 , A61K2800/524 , A61Q5/00 , A61Q11/00 , A61Q17/005 , A61Q19/00 , C07H21/02 , C09D5/025 , C09D5/14 , C11D3/0078 , C11D3/2034 , C11D3/38654 , C11D3/48 , C12N2740/16021 , C12N2740/16122 , C12N2740/16222 , C12N2740/16322 , C12Q1/703 , A01N2300/00
摘要： The nucleotide sequences of the genomes of eleven molecular clones for non-subtype B isolates of human immunodeficiency virus type 1 are disclosed. The invention relates to the nucleic acids and peptides encoded by and/or derived from these sequences and their use in diagnostic methods and as immunogens.

10. 发明申请

US20050033846A1 Resource manager architecture 有权
公开(公告)号：US20050033846A1
公开(公告)日：2005-02-10
申请号：US10930573
申请日：2004-08-31
申请人： Mukund Sankaranarayan , Forrest Foltz , George Shaw , Dale Sather , Andy Raffman , Jai Srinivasan , Terje Backman , William Parry , David Bakin , Michael Jones , Sean McDowell , Jayachandran Raja , Robin Speed
发明人： Mukund Sankaranarayan , Forrest Foltz , George Shaw , Dale Sather , Andy Raffman , Jai Srinivasan , Terje Backman , William Parry , David Bakin , Michael Jones , Sean McDowell , Jayachandran Raja , Robin Speed
IPC分类号： G06F9/52 , G06F9/46 , G06F9/50 , G06F15/173
CPC分类号： G06F9/50 , G06F9/526 , G06F2209/5014 , G06F2209/522 , H04N21/4424 , H04N21/443
摘要： Resource management architectures implemented in computer systems to manage resources are described. In one embodiment, a general architecture includes a resource manager and multiple resource providers that support one or more resource consumers such as a system component or application. Each provider is associated with a resource and acts as the manager for the resource when interfacing with the resource manager. The resource manager arbitrates access to the resources provided by the resource providers on behalf of the consumers. A policy manager sets various policies that are used by the resource manager to allocate resources. One policy is a priority-based policy that distinguishes among which applications and/or users have priority over others to use the resources. A resource consumer creates an “activity” at the resource manager and builds one or more “configurations” that describe various sets of preferred resources required to perform the activity. Each resource consumer can specify one or more configurations for each activity. If multiple configurations are specified, the resource consumer can rank them according to preference. This allows the resource consumers to be dynamically changed from one configuration to another as operating conditions change.

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