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1. 发明授权

US07502978B2 Systems and methods for reconfiguring scan chains 有权
标题翻译：用于重新配置扫描链的系统和方法
公开(公告)号：US07502978B2
公开(公告)日：2009-03-10
申请号：US11314570
申请日：2005-12-21
申请人： John Bratt , Jeffrey Rearick
发明人： John Bratt , Jeffrey Rearick
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.
摘要翻译：提供了重新配置扫描链的系统和方法。代表性系统包括以正常模式或旋转模式操作的触发器的第一扫描链，使得如果第一扫描链在正常模式下操作，则按顺序向触发器提供输入，触发器中的第一触发器在第二触发器之前接收输入，并且如果第一扫描链在旋转模式下操作，则将触发器中的第一触发器接收到输入在第二个触发器之后的输入。

2. 发明申请

US20060156139A1 Systems and methods for facilitating testing of integrated circuits 审中-公开
标题翻译：用于促进集成电路测试的系统和方法
公开(公告)号：US20060156139A1
公开(公告)日：2006-07-13
申请号：US11311013
申请日：2005-12-19
申请人： John Rohrbaugh , Jeffrey Rearick
发明人： John Rohrbaugh , Jeffrey Rearick
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31905 , G01R31/3172 , G01R31/31926
摘要： Systems and methods for testing integrated circuits (ICs) are provided. In this regard, a representative method involves an IC having a first pad configured as a signal interface for components external to the IC, the first pad having a first receiver configured to receive an input signal from a component external to the IC. The method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one stimulus such that the IC detects a presence of a signal short between the first pad and the second pad; and receiving information corresponding to the signal short.
摘要翻译：提供了用于测试集成电路（IC）的系统和方法。在这方面，代表性的方法涉及具有被配置为用于IC外部的组件的信号接口的第一焊盘的IC，第一焊盘具有被配置为从IC外部的部件接收输入信号的第一接收器。该方法包括：将自动测试设备（ATE）与IC互连; 提供至少一个刺激，使得IC检测在第一焊盘和第二焊盘之间存在短路的信号; 并且接收对应于信号短的信息。

3. 发明申请

US20060150040A1 Systems and methods for reconfiguring scan chains 有权
公开(公告)号：US20060150040A1
公开(公告)日：2006-07-06
申请号：US11314570
申请日：2005-12-21
申请人： John Bratt , Jeffrey Rearick
发明人： John Bratt , Jeffrey Rearick
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.

4. 发明申请

US20050229056A1 Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC) 有权
标题翻译：用于比较集成电路（IC）中的功能和AC扫描测试之间的电路性能的电路和方法
公开(公告)号：US20050229056A1
公开(公告)日：2005-10-13
申请号：US10818866
申请日：2004-04-06
申请人： John Rohrbaugh , Jeffrey Rearick
发明人： John Rohrbaugh , Jeffrey Rearick
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318566 , G01R31/318577 , G01R31/31858
摘要： A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), comprises an IC logic element, a scan chain, and a calibration circuit comprising a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.
摘要翻译：用于确定与集成电路（IC）相关联的时钟的操作速度的电路和方法包括IC逻辑元件，扫描链和包括第一多个触发器和组合延迟线的校准电路。校准电路在功能测试模式和扫描测试模式下工作，以确定功能测试模式和扫描测试模式之间的时钟信号延迟。

5. 发明申请

US20070143047A1 Testing target resistances in circuit assemblies 有权
标题翻译：测试电路组件中的目标电阻
公开(公告)号：US20070143047A1
公开(公告)日：2007-06-21
申请号：US11581203
申请日：2006-10-13
申请人： Jeffrey Rearick , Jacob Bell
发明人： Jeffrey Rearick , Jacob Bell
IPC分类号： G01R27/00
CPC分类号： G01R31/2818 , G01R31/31712
摘要： A test system includes a circuit assembly having an IC and an external circuit. The IC comprises test circuitry used to observe data indicative of target resistances in the external circuit. The test system evaluates the data to determine target resistance values. A first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit. A second embodiment enables logic contention on the IC, controllably fixes a pull-down element on the IC, and controllably sweeps a pull-up element on the IC until the voltage at a node between the pull-down and pull-up elements and coupled to an external circuit exceeds a reference voltage.
摘要翻译：测试系统包括具有IC和外部电路的电路组件。该IC包括用于观察表示外部电路中的目标电阻的数据的测试电路。测试系统评估数据以确定目标电阻值。第一实施例测量响应于时变参考电压的两个输出电压。两个输出电压可用于确定外部电路中的电阻值。第二个实施例使得IC上的逻辑争用可控地固定在IC上的下拉元件，并且可控地扫描IC上的上拉元件，直到在下拉和上拉元件之间的节点处的电压并耦合到外部电路超过参考电压。

6. 发明申请

US20060150136A1 Systems and methods for designing integrated circuits 审中-公开
标题翻译：设计集成电路的系统和方法
公开(公告)号：US20060150136A1
公开(公告)日：2006-07-06
申请号：US11314569
申请日：2005-12-21
申请人： John Bratt , Brett William , Jeffrey Rearick
发明人： John Bratt , Brett William , Jeffrey Rearick
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5068
摘要： Systems and methods for designing integrated circuits (ICs) are provided. A representative method includes: providing a netlist; determining components required to implement test of at least a portion of the integrated circuit defined by the netlist; provide a revised netlist including the components determined; and performing a place and route operation with respect to the revised netlist.
摘要翻译：提供了设计集成电路（IC）的系统和方法。代表性的方法包括：提供网表; 确定实现由网表定义的集成电路的至少一部分的测试所需的组件; 提供修订的网表，包括确定的成分; 以及对所修改的网表执行地点和路线操作。

7. 发明申请

US20060139023A1 Delay-locked loop and a method of testing a delay-locked loop 失效
公开(公告)号：US20060139023A1
公开(公告)日：2006-06-29
申请号：US11351173
申请日：2006-02-09
申请人： Alvin Sun Loke , Michael Gilsdorf , Peter Meier , Jeffrey Rearick
发明人： Alvin Sun Loke , Michael Gilsdorf , Peter Meier , Jeffrey Rearick
IPC分类号： G01R23/175
CPC分类号： H03L7/07 , H03L7/0812
摘要： A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

8. 发明申请

US20050222795A1 Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) 失效
标题翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法
公开(公告)号：US20050222795A1
公开(公告)日：2005-10-06
申请号：US10818884
申请日：2004-04-06
申请人： Richard Rodgers , Jeffrey Rearick , Cory Groth
发明人： Richard Rodgers , Jeffrey Rearick , Cory Groth
IPC分类号： G01R31/3185 , G06F19/00
CPC分类号： G01R31/318552 , G01R31/31858
摘要： An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.
摘要翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法包括以寻求确定IC操作的频率（f> TARGET ）操作与IC相关联的时钟，在时钟输出端测量实际时钟周期（T - OUT> ），对IC进行扫描测试，测量实际时钟周期（T _{SCAN - - / SUB> 在时钟输出端，通过计算T SCAN < SUB> CLOCK _{> 和T - _{OUT ，并通过在扫描测试期间增加时钟频率来补偿延迟。}}}

9. 发明申请

US20060167645A1 Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) 有权
标题翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法
公开(公告)号：US20060167645A1
公开(公告)日：2006-07-27
申请号：US11389971
申请日：2006-03-27
申请人： Richard Rogers , Jeffrey Rearick , Cory Groth
发明人： Richard Rogers , Jeffrey Rearick , Cory Groth
IPC分类号： G01R27/28
CPC分类号： G01R31/318552 , G01R31/31858
摘要： An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.
摘要翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法包括以寻求确定IC操作的频率（f> TARGET ）操作与IC相关联的时钟，在时钟输出端测量实际时钟周期（T - OUT> ），对IC进行扫描测试，测量实际时钟周期（T _{SCAN - - / SUB> 在时钟输出端，通过计算T SCAN < SUB> CLOCK _{> 和T - _{OUT ，并通过在扫描测试期间增加时钟频率来补偿延迟。}}}

10. 发明申请

US20060123305A1 Method and apparatus for an embedded time domain reflectometry test 有权
公开(公告)号：US20060123305A1
公开(公告)日：2006-06-08
申请号：US10996113
申请日：2004-11-23
申请人： David Linam , Jeffrey Rearick , Guy Humphrey
发明人： David Linam , Jeffrey Rearick , Guy Humphrey
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/11 , G01R31/31717 , G01R31/31855 , G01R31/318572
摘要： A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

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