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1. 发明申请

US20070049010A1 Disposable pillars for contact formation 有权
标题翻译：接触形成的一次性支柱
公开(公告)号：US20070049010A1
公开(公告)日：2007-03-01
申请号：US11217980
申请日：2005-09-01
申请人： Byron Burgess , John Zahurak
发明人： Byron Burgess , John Zahurak
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/336 , H01L21/8242
CPC分类号： H01L21/76897 , H01L21/0332 , H01L21/31055 , H01L21/31116 , H01L21/3212 , H01L21/823475 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/1052 , H01L27/1085 , H01L27/10888 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
摘要翻译：公开了用于在集成电路中形成触点的牺牲插头以及在集成电路阵列中形成连接的方法。可以使用各种图案转移和蚀刻步骤来创建密集堆叠的特征以及特征之间的连接。牺牲材料可以以跨越字线的连续的之字形线图案被图案化。平面化可以产生平行四边形的材料块，其可以覆盖有源区域以形成牺牲插塞，其可以用导电材料代替以形成接触。

2. 发明申请

US20120153357A1 CONTACT INTEGRATION FOR THREE-DIMENSIONAL STACKING SEMICONDUCTOR DEVICES 有权
标题翻译：三维堆叠半导体器件的接触集成
公开(公告)号：US20120153357A1
公开(公告)日：2012-06-21
申请号：US12969975
申请日：2010-12-16
申请人： Sanh D. Tang , John Zahurak , Shane Trapp , Krishna K. Parat
发明人： Sanh D. Tang , John Zahurak , Shane Trapp , Krishna K. Parat
IPC分类号： H01L23/538 , H01L21/82
CPC分类号： H01L21/8221 , H01L27/0688
摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.
摘要翻译：简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。

3. 发明申请

US20070141821A1 Method of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法
公开(公告)号：US20070141821A1
公开(公告)日：2007-06-21
申请号：US11704488
申请日：2007-02-09
申请人： Kunal Parekh , John Zahurak
发明人： Kunal Parekh , John Zahurak
IPC分类号： H01L21/44
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与在晶体管的栅极附近的各向异性蚀刻的侧壁间隔开。

4. 发明申请

US20060234469A1 A method of forming semiconductor structures 审中-公开
标题翻译：一种形成半导体结构的方法
公开(公告)号：US20060234469A1
公开(公告)日：2006-10-19
申请号：US11409134
申请日：2006-04-21
申请人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
发明人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

5. 发明申请

US20050142703A1 Dual-gate transistor device and method of forming a dual-gate transistor device 有权
标题翻译：双栅极晶体管器件和形成双栅极晶体管器件的方法
公开(公告)号：US20050142703A1
公开(公告)日：2005-06-30
申请号：US10932192
申请日：2004-09-01
申请人： John Zahurak , Brent Keeth , Charles Dennison
发明人： John Zahurak , Brent Keeth , Charles Dennison
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

6. 发明申请

US20110149656A1 MULTI-CELL VERTICAL MEMORY NODES 有权
标题翻译：多个立体声存储器
公开(公告)号：US20110149656A1
公开(公告)日：2011-06-23
申请号：US12646847
申请日：2009-12-23
申请人： Sanh D. Tang , Nishant Sinha , John Zahurak
发明人： Sanh D. Tang , Nishant Sinha , John Zahurak
IPC分类号： G11C16/04 , H01L29/788 , H01L21/84 , H01L21/336
CPC分类号： H01L27/11551 , G11C16/0458 , G11C16/0483 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.
摘要翻译：本发明的实施例涉及垂直存储器结构。本发明的实施例描述了在分离源区和漏区的垂直沟道的相对侧上包括两个存储单元的存储器节点。本发明的实施例可以利用浮动栅极NAND存储器单元，多晶硅二极管，MiM二极管或者MiiM二极管。本发明的实施例可用于形成闪速存储器，RRAM，忆阻器RAM，氧化物Ram或OTPROM。

7. 发明申请

US20060228893A1 Semiconductor substrates and field effect transistor constructions 有权
标题翻译：半导体衬底和场效应晶体管结构
公开(公告)号：US20060228893A1
公开(公告)日：2006-10-12
申请号：US11448257
申请日：2006-06-06
申请人： John Zahurak , David Hwang
发明人： John Zahurak , David Hwang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/4933 , H01L29/6656 , H01L29/7833
摘要： The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise a gate dielectric layer and a conductive metal-comprising layer having an ion implanted polysilicon layer received therebetween. Patterned masking material is formed over the series of layers. Using the patterned masking material as a mask, etching is conducted through the conductive metal-comprising layer and only partially into the ion implanted polysilicon layer. After such etching, the ion implanted polysilicon is annealed effective to electrically activate implanted impurity atoms received therein. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成场效应晶体管栅极的方法。在一个实现中，在半导体材料沟道区域附近形成一系列层。这些层包括栅极电介质层和在其间容纳离子注入的多晶硅层的导电金属层。在一系列层上形成图案化掩模材料。使用图案化掩模材料作为掩模，通过导电金属包层进行蚀刻，并且仅部分地进入离子注入的多晶硅层。在这种蚀刻之后，离子注入的多晶硅被退火有效地电激活其中接收的注入杂质原子。考虑了其他方面和实现。

8. 发明申请

US20050181567A1 Double blanket ion implant method and structure 审中-公开
标题翻译：双层离子注入法和结构
公开(公告)号：US20050181567A1
公开(公告)日：2005-08-18
申请号：US11094377
申请日：2005-03-31
申请人： Mark Fischer , Charles Dennison , Fawad Ahmed , Richard Lane , John Zahurak , Kunal Parekh
发明人： Mark Fischer , Charles Dennison , Fawad Ahmed , Richard Lane , John Zahurak , Kunal Parekh
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/2652 , H01L21/2658 , H01L21/28247 , H01L29/6656 , H01L29/6659
摘要： A double blanket ion implant method for forming diffulsion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffulsion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成差分区域的双层离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对差分区域。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

9. 发明申请

US20050032284A1 Localized biasing for silicon on insulator structures 有权
标题翻译：硅绝缘体结构的局部偏置
公开(公告)号：US20050032284A1
公开(公告)日：2005-02-10
申请号：US10930001
申请日：2004-08-30
申请人： Fernando Gonzalez , John Zahurak
发明人： Fernando Gonzalez , John Zahurak
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/02 , H01L27/12
CPC分类号： H01L21/84 , H01L27/0214 , H01L27/10858 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
摘要翻译：绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。导体连接到偏置电压源。在一个实施例中，提供分别连接到多个电压源的多个导体。因此，硅层的不同区域被不同的偏置信号偏置。

10. 发明授权

US08735902B2 Memories with memory arrays extending in opposite directions from a semiconductor and their formation 有权
标题翻译：具有从半导体沿相反方向延伸的存储器阵列及其形成的存储器
公开(公告)号：US08735902B2
公开(公告)日：2014-05-27
申请号：US12776965
申请日：2010-05-10
申请人： Sanh D. Tang , John Zahurak , Siddartha Kondoju , Haitao Liu , Nishant Sinha
发明人： Sanh D. Tang , John Zahurak , Siddartha Kondoju , Haitao Liu , Nishant Sinha
IPC分类号： H01L21/8239
CPC分类号： H01L27/11293 , H01L21/823885 , H01L27/0688 , H01L27/101 , H01L27/105 , H01L27/1052 , H01L27/11206 , H01L27/11517 , H01L27/11524 , H01L27/11551 , H01L27/11563 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.
摘要翻译：记忆及其形成被披露。一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。两个阵列可以是非易失性存储器阵列。例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。

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