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1. 发明申请

US20050142703A1 Dual-gate transistor device and method of forming a dual-gate transistor device 有权
标题翻译：双栅极晶体管器件和形成双栅极晶体管器件的方法
公开(公告)号：US20050142703A1
公开(公告)日：2005-06-30
申请号：US10932192
申请日：2004-09-01
申请人： John Zahurak , Brent Keeth , Charles Dennison
发明人： John Zahurak , Brent Keeth , Charles Dennison
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

2. 发明授权

US06757200B2 Semiconductor memory having dual port cell supporting hidden refresh 失效
标题翻译：具有双端口单元的半导体存储器支持隐藏刷新
公开(公告)号：US06757200B2
公开(公告)日：2004-06-29
申请号：US10269599
申请日：2002-10-10
申请人： Brent Keeth , Charles Dennison
发明人： Brent Keeth , Charles Dennison
IPC分类号： G11C700
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.
摘要翻译：本发明涉及具有用于存储数据的存储单元的集成电路装置和用于刷新存储单元中的数据的刷新电路。在一个说明性实施例中，该设备包括具有存储元件，读/写访问设备和刷新访问设备的存储单元。读/写数字线耦合到读/写访问设备，并且刷新数字线耦合到刷新访问设备。读出放大器耦合到读/写数字线，并且输入/输出电路耦合到读/写数字线。刷新读出放大器耦合到刷新数字线。存储单元被构造成在相对较小，紧凑的区域中提供大的电荷存储容量。

3. 发明申请

US20070055818A1 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US20070055818A1
公开(公告)日：2007-03-08
申请号：US11595370
申请日：2006-11-08
申请人： Brent Keeth , Brian Shirley , Charles Dennison
发明人： Brent Keeth , Brian Shirley , Charles Dennison
IPC分类号： G06F13/28
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM. By the time data have been stored in the SRAM, the SRAM previously used to store write data has transferred the data to the first DRAM bank and in thus available to store a subsequent write. Therefore, an SRAM bank is always available to store write data in the event the DRAM bank to which the data are directed is being refreshed.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，每个存储体可以在刷新控制器的控制下刷新。除了DRAM的通常部件之外，高速缓冲存储器系统还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传送期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体中。然而，如果第二个银行被刷新，则数据被存储在另一个SRAM中。在数据已经存储在SRAM中的时候，先前用于存储写入数据的SRAM已将数据传送到第一DRAM存储体，并因此可用于存储随后的写入。因此，在刷新数据所指向的DRAM组的情况下，SRAM存储体总是可用于存储写入数据。

4. 发明申请

US20060015679A1 Method and system for using dynamic random access memory as cache memory 有权
公开(公告)号：US20060015679A1
公开(公告)日：2006-01-19
申请号：US11230836
申请日：2005-09-19
申请人： Brent Keeth , Brian Shirley , Charles Dennison
发明人： Brent Keeth , Brian Shirley , Charles Dennison
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

5. 发明授权

US06438016B1 Semiconductor memory having dual port cell supporting hidden refresh 失效
标题翻译：具有双端口单元的半导体存储器支持隐藏刷新
公开(公告)号：US06438016B1
公开(公告)日：2002-08-20
申请号：US10027569
申请日：2001-10-19
申请人： Brent Keeth , Charles Dennison
发明人： Brent Keeth , Charles Dennison
IPC分类号： G11C506
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.
摘要翻译：本发明涉及具有用于存储数据的存储单元的集成电路装置和用于刷新存储单元中的数据的刷新电路。在一个说明性实施例中，该设备包括具有存储元件，读/写访问设备和刷新访问设备的存储单元。读/写数字线耦合到读/写访问设备，并且刷新数字线耦合到刷新访问设备。读出放大器耦合到读/写数字线，并且输入/输出电路耦合到读/写数字线。刷新读出放大器耦合到刷新数字线。存储单元被构造成在相对较小，紧凑的区域中提供大的电荷存储容量。

6. 发明申请

US20210240344A1 WAFER-SCALE MEMORY TECHNIQUES 有权
公开(公告)号：US20210240344A1
公开(公告)日：2021-08-05
申请号：US17162796
申请日：2021-01-29
申请人： Brent Keeth , Bambi L. DeLaRosa , Eiichi Nakano
发明人： Brent Keeth , Bambi L. DeLaRosa , Eiichi Nakano
IPC分类号： G06F3/06
摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

7. 发明申请

US20210200464A1 MEMORY DEVICE INTERFACE AND METHOD 有权
公开(公告)号：US20210200464A1
公开(公告)日：2021-07-01
申请号：US17136728
申请日：2020-12-29
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G06F3/06
摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

8. 发明授权

US09214449B2 Reconfigurable connections for stacked semiconductor devices 有权
标题翻译：层叠半导体器件的可重构连接
公开(公告)号：US09214449B2
公开(公告)日：2015-12-15
申请号：US13367026
申请日：2012-02-06
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/26 , H01L25/065 , G11C5/02 , G11C5/06 , G11C29/02 , G11C29/00 , G11C5/04 , G11C29/32
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接的缺陷。

9. 发明授权

US08712249B2 Optical interconnect in high-speed memory systems 有权
标题翻译：高速存储器系统中的光互连
公开(公告)号：US08712249B2
公开(公告)日：2014-04-29
申请号：US13080376
申请日：2011-04-05
申请人： Russel J. Baker , Brent Keeth
发明人： Russel J. Baker , Brent Keeth
IPC分类号： H04B10/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/1668 , G06F13/287 , G06F13/4234 , G11C11/42 , H04B10/802 , H04L12/40013 , H04Q11/0071 , Y02D10/14 , Y02D10/151
摘要： A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.
摘要翻译：公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。

10. 发明申请

US20120246434A1 SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
标题翻译：基于命令信号和操作状态解码命令的系统和方法
公开(公告)号：US20120246434A1
公开(公告)日：2012-09-27
申请号：US13489246
申请日：2012-06-05
申请人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
发明人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
IPC分类号： G06F12/00
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译：一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。

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