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1. 发明申请

US20190067028A1 VAPOR-ETCH CYCLIC PROCESS 审中-公开
公开(公告)号：US20190067028A1
公开(公告)日：2019-02-28
申请号：US15686526
申请日：2017-08-25
申请人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
发明人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
IPC分类号： H01L21/311 , H01L21/02 , H01L27/108 , H01L21/66 , H01L21/67
摘要： Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

2. 发明授权

US08574954B2 Phase change memory structures and methods 有权
标题翻译：相变记忆结构和方法
公开(公告)号：US08574954B2
公开(公告)日：2013-11-05
申请号：US12872945
申请日：2010-08-31
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： H01L21/62
CPC分类号： H01L45/1253 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.
摘要翻译：本文描述了与相变材料存储器相关联的方法，装置和系统。在一个或多个实施例中，形成相变材料存储单元的方法包括形成多个存储器结构区域，其中存储器结构区域包括底部电极材料和牺牲材料，在多个绝缘体区域之间形成多个绝缘体区域存储器结构区域，在多个绝缘体区域之间形成多个开口，并通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成轮廓表面，在数量上形成多个电介质间隔物的绝缘体区域之间，在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分电介质间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。

3. 发明授权

US08535992B2 Thyristor random access memory device and method 有权
标题翻译：晶闸管随机存取存储器件及方法
公开(公告)号：US08535992B2
公开(公告)日：2013-09-17
申请号：US12826323
申请日：2010-06-29
申请人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
发明人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
IPC分类号： H01L21/322
CPC分类号： H01L29/66363 , H01L27/1027 , H01L29/42308 , H01L29/74 , H01L2924/1301
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

4. 发明授权

US08513722B2 Floating body cell structures, devices including same, and methods for forming same 有权
标题翻译：浮体细胞结构，包括其的装置及其形成方法
公开(公告)号：US08513722B2
公开(公告)日：2013-08-20
申请号：US12715843
申请日：2010-03-02
申请人： Sanh D. Tang , John K. Zahurak , Werner Juengling
发明人： Sanh D. Tang , John K. Zahurak , Werner Juengling
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10802 , H01L21/845 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/4236 , H01L29/7841
摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.
摘要翻译：包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。还公开了形成浮体电池器件的方法。

5. 发明授权

US08501559B2 Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same 有权
公开(公告)号：US08501559B2
公开(公告)日：2013-08-06
申请号：US13610513
申请日：2012-09-11
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L21/8234
CPC分类号： H01L21/762 , H01L21/32 , H01L27/0814 , H01L27/108 , H01L27/10808 , H01L27/2454 , H01L27/2472 , H01L29/66666 , H01L29/7827 , H01L29/861 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

6. 发明授权

US08440515B2 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US08440515B2
公开(公告)日：2013-05-14
申请号：US12191119
申请日：2008-08-13
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

7. 发明授权

US08394699B2 Memory arrays and methods of fabricating memory arrays 有权
标题翻译：存储器阵列和制造存储器阵列的方法
公开(公告)号：US08394699B2
公开(公告)日：2013-03-12
申请号：US12828915
申请日：2010-07-01
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66621 , G11C11/405 , H01L27/10823 , H01L27/10844 , H01L27/10876 , H01L27/10891
摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
摘要翻译：存储器阵列包括形成在半导体衬底上的多个存储单元。存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。第一和第二场效应晶体管的栅极被硬连线在一起。导电数据线硬连接到两个源极/漏极区域。电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。考虑了其他方面和实现方式，包括制造存储器阵列的方法。

8. 发明申请

US20130011974A1 Thyristor-Based Memory Cells, Devices and Systems Including the Same and Methods for Forming the Same 有权
公开(公告)号：US20130011974A1
公开(公告)日：2013-01-10
申请号：US13610034
申请日：2012-09-11
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： H01L21/332
CPC分类号： H01L27/1027 , H01L21/28088 , H01L21/32051 , H01L21/32055 , H01L21/32133 , H01L29/401 , H01L29/42308 , H01L29/66363 , H01L29/749
摘要： Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

9. 发明申请

US20130005100A1 Semiconductor Cells, Arrays, Devices and Systems Having a Buried Conductive Line and Methods for Forming the Same 有权
公开(公告)号：US20130005100A1
公开(公告)日：2013-01-03
申请号：US13610513
申请日：2012-09-11
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L21/336
CPC分类号： H01L21/762 , H01L21/32 , H01L27/0814 , H01L27/108 , H01L27/10808 , H01L27/2454 , H01L27/2472 , H01L29/66666 , H01L29/7827 , H01L29/861 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

10. 发明申请

US20120238061A1 Methods Of Forming Transistors, And Methods Of Forming Memory Arrays 有权
标题翻译：形成晶体管的方法，以及形成记忆阵列的方法
公开(公告)号：US20120238061A1
公开(公告)日：2012-09-20
申请号：US13485892
申请日：2012-05-31
申请人： Mark Fischer , Sanh D. Tang
发明人： Mark Fischer , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/823425 , H01L21/823487 , H01L27/2454 , H01L29/0653 , H01L29/42368 , H01L29/456 , H01L29/66666 , H01L29/7827 , H01L45/06 , H01L45/1233
摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
摘要翻译：一些实施例包括形成垂直晶体管的方法。结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域渠道区域位置。导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

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