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1. 发明授权

US07089947B2 Apparatus and method for cleaning a semiconductor wafer 失效
公开(公告)号：US07089947B2
公开(公告)日：2006-08-15
申请号：US10383607
申请日：2003-03-10
申请人： In-jun Yeo , Byoung-moon Yoon , Kyung-hyun Kim , Sang-rok Hah , Jeong-lim Nam , Hyun-ho Jo
发明人： In-jun Yeo , Byoung-moon Yoon , Kyung-hyun Kim , Sang-rok Hah , Jeong-lim Nam , Hyun-ho Jo
IPC分类号： B08B6/00
CPC分类号： H01L21/67051 , B08B3/12 , Y10S134/902
摘要： The apparatus for cleaning a wafer includes an energy concentration relieving member positioned at the side of the wafer. An elongated portion of a probe extends over and substantially parallel to the wafer surface. A vibrator is attached to a rear end of the probe for vibrating the probe such that the elongated portion transfers acoustic vibrational energy to the wafer and dislodges debris.

2. 发明授权

US07017597B2 Megasonic cleaning apparatus for fabricating semiconductor device 失效
公开(公告)号：US07017597B2
公开(公告)日：2006-03-28
申请号：US10217006
申请日：2002-08-12
申请人： Byoung-moon Yoon , In-jun Yeo , Sang-rok Hah , Kyung-hyun Kim , Hyun-ho Jo , Jeong-lim Nam
发明人： Byoung-moon Yoon , In-jun Yeo , Sang-rok Hah , Kyung-hyun Kim , Hyun-ho Jo , Jeong-lim Nam
IPC分类号： B09B3/10
CPC分类号： H01L21/67051 , B08B3/12 , Y10S134/902
摘要： A megasonic cleaning apparatus is provided for removing contamination particles on a wafer. The megasonic cleaning apparatus includes a piezoelectric transducer and an energy transfer rod. The piezoelectric transducer is for generating megasonic energy. The energy transfer rod installed over the wafer along a radial direction of the wafer is for distributing the megasonic energy to cleaning solution over the wafer and for vibrating the cleaning solution. The energy transfer rod is shaped and sized to uniformly distribute energy in the radial direction of the wafer through the cleaning solution to remove the contamination particles from the wafer.

3. 发明授权

US07687369B2 Method of forming fine metal patterns for a semiconductor device using a damascene process 有权
标题翻译：使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
公开(公告)号：US07687369B2
公开(公告)日：2010-03-30
申请号：US11896512
申请日：2007-09-04
申请人： Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
发明人： Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
IPC分类号： H01L21/76
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32115 , H01L21/32134
摘要： A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
摘要翻译：一种形成精细金属互连图案的方法包括在基板上形成绝缘膜，在绝缘膜上形成多个模具图案，其间具有第一间隔，使得模具图案具有第一布局，在第一空间中形成金属硬掩模图案通过镶嵌工艺去除模具图案，通过金属硬掩模图案蚀刻绝缘膜以形成具有第二间隔的绝缘膜图案，第二空间具有第一布局，并且在第二空间中形成具有第一布局的金属互连图案通过大马士革的过程。

4. 发明授权

US08278221B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US08278221B2
公开(公告)日：2012-10-02
申请号：US13181655
申请日：2011-07-13
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

5. 发明授权

US08003543B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US08003543B2
公开(公告)日：2011-08-23
申请号：US12759771
申请日：2010-04-14
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

6. 发明申请

US20080090419A1 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20080090419A1
公开(公告)日：2008-04-17
申请号：US11727124
申请日：2007-03-23
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

7. 发明授权

US06841338B2 Photoresist composition and method of forming a photoresist pattern with a controlled remnant ratio 有权
标题翻译：光刻胶组合物和形成具有受控残留比的光致抗蚀剂图案的方法
公开(公告)号：US06841338B2
公开(公告)日：2005-01-11
申请号：US10173375
申请日：2002-06-17
申请人： Dae-youp Lee , Jeong-lim Nam , Do-yul Yoo , Jeung-woo Lee
发明人： Dae-youp Lee , Jeong-lim Nam , Do-yul Yoo , Jeung-woo Lee
IPC分类号： C08F212/14 , G03F1/14 , G03F7/004 , G03F7/039 , G03F7/30 , G03F7/32 , G03F7/40 , H01L21/027 , G03C5/00
CPC分类号： G03F7/0392 , G03F1/50
摘要： A photoresist composition may include formulas 1 and 2: where R is an acetal group or a ter-butyloxy carbonyl (t-BOC) group, n and m are integers, n/(m+n) is 0.01−0.8, and m/(m+n) is 1−[n/(m+n)], where r is an integer between 8-40. A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.
摘要翻译：光致抗蚀剂组合物可以包括式1和2：其中R是缩醛基或叔丁氧基羰基（t-BOC）基团，n和m是整数，n /（m + n）是0.01-0.8，m / （m + n）是1- [n /（m + n）]，其中r是8-40之间的整数。一种用于形成光致抗蚀剂图案的方法可以包括在半导体衬底上形成光致抗蚀剂层并曝光和显影光致抗蚀剂层，其使用包括具有约100％的光透射率的第一区域和具有约10％至约30％的透光率的第二区域的掩模图案。

8. 发明授权

US06372042B1 System for processing semiconductor wafers producing a downward laminar flow of clean air in front of baking units 失效
标题翻译：用于处理半导体晶片的系统，其在烘烤单元前面产生清洁空气的向下层流
公开(公告)号：US06372042B1
公开(公告)日：2002-04-16
申请号：US09482537
申请日：2000-01-14
申请人： Woo-dong Sung , Sam-soon Han , Chang-wook Oh , Jeong-lim Nam
发明人： Woo-dong Sung , Sam-soon Han , Chang-wook Oh , Jeong-lim Nam
IPC分类号： B05C1102
CPC分类号： H01L21/67034
摘要： A photo process system for semiconductor wafers prevents air from flowing across the top of a baking region to produce a stable downward laminar air flow in front of baking units disposed at several levels in the baking region. The baking region is located on one side of a housing, and a coating unit for coating a wafer with a photoresist is located on the other side of the housing. The housing has a clean air entrance and air filters at an upper portion thereof, and a clean air discharge opening at the very bottom thereof. An air flow containment dam prevents clean air entering the housing from flowing horizontally at the top of the baking region. Such a horizontal flow of air would otherwise produce turbulence severely affecting the ability of the air to flow downward across the front of the baking units and toward the discharge opening as a laminar air flow. The laminar air flow hardly passes into the baking units and thus, hardly induces temperature variations in the coated wafers that are being baked. Accordingly, the thickness of the photoresist film on the wafer becomes highly uniform, as does the critical dimension of a pattern produced from the film. Also, dust or ionic contaminants are directly discharged through the discharge opening at the bottom of the housing by the downward laminar flow of clean air. The wafers within the baking units are prevented from being contaminated, thereby enhancing the yield of the semiconductor products.
摘要翻译：用于半导体晶片的照相处理系统防止空气流过烘烤区域的顶部，以在烘烤单元前面设置稳定的向下层流气流，该烘烤单元设置在烘烤区域中的若干水平。烘烤区域位于壳体的一侧，并且用于用光致抗蚀剂涂覆晶片的涂布单元位于壳体的另一侧。壳体在其上部具有清洁空气入口和空气过滤器，并且在其最底部具有清洁空气排出口。一个气流容纳挡板防止进入壳体的清洁空气在烘烤区域的顶部水平流动。这样的水平空气流动否则将产生严重影响空气沿烘烤单元的前部向下流动并且以层流空气流向排放口的能力的湍流。层流气流几乎不会进入烘焙单元，因此几乎不会引起被烘烤的涂覆的晶片的温度变化。因此，晶片上的光致抗蚀剂膜的厚度变得高度均匀，与由膜产生的图案的临界尺寸一样。此外，灰尘或离子污染物通过清洁空气的向下层流直接排出通过壳体底部的排放口。防止烘烤单元内的晶片被污染，从而提高半导体产品的产量。

9. 发明申请

US20110269294A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20110269294A1
公开(公告)日：2011-11-03
申请号：US13181655
申请日：2011-07-13
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

10. 发明申请

US20100197139A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20100197139A1
公开(公告)日：2010-08-05
申请号：US12759771
申请日：2010-04-14
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

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