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1. 发明授权

US08338310B2 Method of forming line/space patterns 失效
标题翻译：形成线/空格的方法
公开(公告)号：US08338310B2
公开(公告)日：2012-12-25
申请号：US12786466
申请日：2010-05-25
申请人： Sung-gon Jung , Suk-joo Lee , Woo-sung Han , Seong-woon Choi
发明人： Sung-gon Jung , Suk-joo Lee , Woo-sung Han , Seong-woon Choi
IPC分类号： H01L21/301
CPC分类号： H01L21/3086 , H01L27/105 , H01L27/115 , H01L27/11517
摘要： A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and the remaining second pattern structures as an etch mask, and etching the substrate using the hard mask as an etch mask.
摘要翻译：形成线/空间图案的方法包括在设置在基板上的硬掩模材料层上形成多个第一图案结构，沿着第一图案结构的侧壁形成多个第二图案结构，将第一图案结构所述第二图案结构在所述硬掩模材料层上独立地形成，形成第一掩模，所述第一掩模暴露要形成的所述线/空间图案的空间的位置的宽度大于所述第二掩模去除由第一掩模曝光的第二图案结构的图案结构，使得其他第二图案结构保留在硬掩模材料层上，形成覆盖线/空间线的位置的第二掩模要形成的图案是具有大于第二图案结构的宽度的宽度，通过蚀刻硬掩模材料层形成硬掩模将第二掩模和剩余的第二图案结构作为蚀刻掩模，并使用硬掩模作为蚀刻掩模蚀刻该衬底。

2. 发明申请

US20120256904A1 LIQUID CRYSTAL DISPLAY, AND DEVICE AND METHOD OF MODIFYING IMAGE SIGNAL FOR LIQUID CRYSTAL DISPLAY 有权
标题翻译：液晶显示器，以及用于液晶显示的图像信号修改装置及方法
公开(公告)号：US20120256904A1
公开(公告)日：2012-10-11
申请号：US13215395
申请日：2011-08-23
申请人： Sung Gon JUNG , Sang Su HAN , Seok Hwan ROH
发明人： Sung Gon JUNG , Sang Su HAN , Seok Hwan ROH
IPC分类号： G06T15/00 , G09G3/36
CPC分类号： G09G3/36 , G09G3/3648 , G09G5/06 , G09G2320/0252 , G09G2320/0285 , G09G2340/02 , G09G2340/16
摘要： An image signal modifying device includes a pixel, a memory which stores compressed information in which a three-dimensional (“3-D”) lookup table is coded, an image signal modifying unit which decodes the compressed information to generate a restored 3-D lookup table and generates a modified signal based on a first image signal of a first frame, a second image signal of a second frame, a third image signal of a third frame and the restored 3-D lookup table, and a data driver which converts the modified signal into the data voltage and supplies the data voltage to the pixel.
摘要翻译：图像信号修改装置包括像素，存储编码了三维（3-D）查找表的压缩信息的存储器，对压缩信息进行解码以生成恢复的3-D查找表的图像信号修改单元并且基于第一帧的第一图像信号，第二帧的第二图像信号，第三帧的第三图像信号和恢复的3-D查找表来生成修改的信号，以及数据驱动器，其将修改的信号进入数据电压并将数据电压提供给像素。

3. 发明申请

US20120206429A1 METHOD OF PROCESSING DATA AND A DISPLAY APPARATUS PERFORMING THE METHOD 有权
标题翻译：处理数据的方法和执行该方法的显示装置
公开(公告)号：US20120206429A1
公开(公告)日：2012-08-16
申请号：US13311769
申请日：2011-12-06
申请人： Sang-Keun Lee , Seung-Seok NAM , Sung-Gon JUNG , Sang-Su HAN
发明人： Sang-Keun Lee , Seung-Seok NAM , Sung-Gon JUNG , Sang-Su HAN
IPC分类号： G06F3/038 , H04L27/00
CPC分类号： H04L25/4902 , G09G3/3614 , G09G3/3648 , G09G5/008 , G09G2370/08 , G09G2370/14
摘要： A method of processing data including dividing, at a transmitter, data into 3-bit units, generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal, transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal, and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal.
摘要翻译：一种处理数据的方法，包括在发射机处将数据划分为3比特单元，在发射机处生成第一和第二时钟嵌入数据信号和第三数据信号，其中包括时钟信号和单元的第一比特在第一时钟嵌入数据信号中，时钟信号和第二位的单元包括在第二时钟嵌入数据信号中，第三位包括在第三数据信号中，从发送器发送到接收器，第一和第二时钟嵌入数据信号和第三数据信号，并且在接收机处恢复来自第一和第二时钟嵌入数据信号的第一和第二位和时钟信号以及来自第三数据信号的第三位。

4. 发明授权

US08193047B2 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US08193047B2
公开(公告)日：2012-06-05
申请号：US12654798
申请日：2010-01-04
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L21/8239
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

5. 发明授权

US07687369B2 Method of forming fine metal patterns for a semiconductor device using a damascene process 有权
标题翻译：使用镶嵌工艺形成用于半导体器件的精细金属图案的方法
公开(公告)号：US07687369B2
公开(公告)日：2010-03-30
申请号：US11896512
申请日：2007-09-04
申请人： Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
发明人： Cha-won Koh , Jeong-lim Nam , Gi-sung Yeo , Sang-jin Kim , Sung-gon Jung
IPC分类号： H01L21/76
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32115 , H01L21/32134
摘要： A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
摘要翻译：一种形成精细金属互连图案的方法包括在基板上形成绝缘膜，在绝缘膜上形成多个模具图案，其间具有第一间隔，使得模具图案具有第一布局，在第一空间中形成金属硬掩模图案通过镶嵌工艺去除模具图案，通过金属硬掩模图案蚀刻绝缘膜以形成具有第二间隔的绝缘膜图案，第二空间具有第一布局，并且在第二空间中形成具有第一布局的金属互连图案通过大马士革的过程。

6. 发明授权

US07604907B2 Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets 有权
标题翻译：多曝光半导体制造掩模组和制造这种多曝光掩模组的方法
公开(公告)号：US07604907B2
公开(公告)日：2009-10-20
申请号：US11243401
申请日：2005-10-04
申请人： Doo-Youl Lee , Seok-Hwan Oh , Gi-Sung Yeo , Sang-Gyun Woo , Sook Lee , Joo-On Park , Sung-Gon Jung
发明人： Doo-Youl Lee , Seok-Hwan Oh , Gi-Sung Yeo , Sang-Gyun Woo , Sook Lee , Joo-On Park , Sung-Gon Jung
IPC分类号： G03F1/00
CPC分类号： G03F7/70466 , G03F1/00
摘要： Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.
摘要翻译：提供掩模组，其可以用于限定在制造半导体器件期间具有第一间距图案的第一图案区域和具有第二间距图案的第二图案区域。这些掩模组可以包括具有第一曝光区域的第一掩模，其中第一半色调图案限定第一图案区域和第一屏蔽区域，其中第一屏蔽层覆盖第二图案区域。这些掩模组还可以包括具有第二曝光区域的第二掩模，其中第二半色调图案限定第二图案区域和第二屏蔽区域，其中第二屏蔽层覆盖第一图案区域。第二屏蔽层也从第二屏幕区域延伸以覆盖第二半色调图案的一部分。

7. 发明授权

US07452825B2 Method of forming a mask structure and method of forming a minute pattern using the same 有权
标题翻译：形成掩模结构的方法和使用其形成微小图案的方法
公开(公告)号：US07452825B2
公开(公告)日：2008-11-18
申请号：US11589372
申请日：2006-10-30
申请人： Doo-Youl Lee , Han-Ku Cho , Suk-Joo Lee , Gi-Sung Yeo , Cha-Won Koh , Sung-Gon Jung
发明人： Doo-Youl Lee , Han-Ku Cho , Suk-Joo Lee , Gi-Sung Yeo , Cha-Won Koh , Sung-Gon Jung
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： H01L21/0337
摘要： In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.
摘要翻译：在形成掩模结构的方法中，第一掩模形成在基板上，其中第一掩模包括具有多个具有开口的掩模图案部分的第一掩模图案和第二掩模图案，第二掩模图案具有内侧弯曲的墙壁牺牲层形成在第一掩模上。在牺牲层上形成硬掩模层。在硬掩模层被部分地去除直到与拐角部分相邻的牺牲层被暴露之后，在去除牺牲层之后从残留在空间中的硬掩模层形成第二掩模。可以容易地在基板上形成具有精细结构的微小图案。

8. 发明申请

US20080057610A1 Method of forming a mask structure and method of forming a minute pattern using the same 有权
公开(公告)号：US20080057610A1
公开(公告)日：2008-03-06
申请号：US11589372
申请日：2006-10-30
申请人： Doo-Youl Lee , Han-Ku Cho , Suk-Joo Lee , Gi-Sung Yeo , Cha-Won Koh , Sung-Gon Jung
发明人： Doo-Youl Lee , Han-Ku Cho , Suk-Joo Lee , Gi-Sung Yeo , Cha-Won Koh , Sung-Gon Jung
IPC分类号： H01L21/00
CPC分类号： H01L21/0337
摘要： In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.

9. 发明申请

US20070190812A1 SEMICONDUCTOR DEVICE HAVING SUFFICIENT PROCESS MARGIN AND METHOD OF FORMING SAME 审中-公开
标题翻译：具有充分过程的半导体器件及其形成方法
公开(公告)号：US20070190812A1
公开(公告)日：2007-08-16
申请号：US11737675
申请日：2007-04-19
申请人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
发明人： Man-Hyoung RYOO , Gi-Sung YEO , Si-Hyeung LEE , Gyu-Chul KIM , Sung-Gon JUNG , Chang-Min PARK , Hoo-Sung CHO
IPC分类号： H01L21/027
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

10. 发明授权

US07221031B2 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US07221031B2
公开(公告)日：2007-05-22
申请号：US10892588
申请日：2004-07-15
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

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