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1. 发明授权

US06715497B2 Treatment to eliminate polysilicon defects induced by metallic contaminants 失效
标题翻译：处理以消除由金属污染物引起的多晶硅缺陷
公开(公告)号：US06715497B2
公开(公告)日：2004-04-06
申请号：US09753283
申请日：2001-01-02
申请人： Brian P. Conchieri , David D. Dussault , Mousa H. Ishaq
发明人： Brian P. Conchieri , David D. Dussault , Mousa H. Ishaq
IPC分类号： B08B600
CPC分类号： H01L21/02046 , B08B7/00 , B08B7/0071 , H01L21/3221
摘要： A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminants on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminants on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.
摘要翻译：提供了一种方法和装置，用于通过将可能在其表面上具有污染物的半导体衬底加热到集成封闭系统内的升高温度，同时清洗半导体衬底的表面上来消除污染物，包括金属和/或含烃污染物综合封闭系统含有含氯气体。在升高的温度下，氯从含氯气体中解离并与衬底表面上的污染物反应，形成具有这种污染物的挥发性氯化物副产物，其从基本上封闭的系统中除去，同时衬底被连续加热并用氯 - 含气。随后，将衬底移动到集成闭合系统内的冷却室，并冷却以提供具有干净表面的半导体衬底。

2. 发明授权

US06855207B2 Apparatus and system for eliminating contaminants on a substrate surface 失效
标题翻译：用于消除基材表面污染物的装置和系统
公开(公告)号：US06855207B2
公开(公告)日：2005-02-15
申请号：US10732578
申请日：2003-12-10
申请人： Brian P. Conchieri , David D. Dussault , Mousa H. Ishaq
发明人： Brian P. Conchieri , David D. Dussault , Mousa H. Ishaq
IPC分类号： B08B7/00 , H01L21/306 , H01L21/322 , H01L21/00
CPC分类号： H01L21/02046 , B08B7/00 , B08B7/0071 , H01L21/3221
摘要： An intergrated closed apparatus and system for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate. The apparatus and system include a heating chamber for heating the contaminated substrate to an elevated temperature, and an input line for purging the chamber with a chlorine-containing gas. The chlorine dissociates from the chlorine-containing gas, reacts with the contaminates, and forms volatile chloride byproducts which are removed from the heating chamber via an output line. A cooling chamber of the apparatus and system having an input line for providing a gas therein cools the substrate. A workpiece holds the substrate, which in turn, is held in position by a pedestal. The pedestal is in contact with a door that seals the closed apparatus and system, whereby the door transfers the substrate from the heating chamber to the cooling chamber, and vice versa.
摘要翻译：一种用于消除在半导体衬底的表面上的包含金属和/或含烃污染物的污染物的集成封闭装置和系统。该装置和系统包括用于将被污染的基底加热至高温的加热室，以及用含氯气体吹扫室的输入管线。氯气与含氯气体分离，与污染物反应，形成挥发性氯化物副产物，通过输出管路从加热室中除去。具有用于提供气体的输入线的装置和系统的冷却室冷却基板。工件保持衬底，衬底又由基座保持就位。基座与密封装置和系统的门接触，由此门将基板从加热室传送到冷却室，反之亦然。

3. 发明申请

US20130248112A1 VACUUM TRAP 有权
公开(公告)号：US20130248112A1
公开(公告)日：2013-09-26
申请号：US13425470
申请日：2012-03-21
申请人： Joseph K. Comeau , David Crawford , Robert E. Desrosiers , Tracy C. Hetrick , Mousa H. Ishaq
发明人： Joseph K. Comeau , David Crawford , Robert E. Desrosiers , Tracy C. Hetrick , Mousa H. Ishaq
IPC分类号： C23F1/08 , B08B7/00
CPC分类号： H01J37/32633 , C23C16/45536 , C23C16/45587 , C23C16/45589 , C23C16/50 , C23F1/00 , F04F9/00 , H01J37/32834 , H01J2237/18 , H01J2237/1825
摘要： A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.

4. 发明授权

US09057388B2 Vacuum trap 有权
标题翻译：真空阱
公开(公告)号：US09057388B2
公开(公告)日：2015-06-16
申请号：US13425470
申请日：2012-03-21
申请人： Joseph K. Comeau , David Crawford , Robert E. Desrosiers , Tracy C. Hetrick , Mousa H. Ishaq
发明人： Joseph K. Comeau , David Crawford , Robert E. Desrosiers , Tracy C. Hetrick , Mousa H. Ishaq
IPC分类号： F04F9/00 , C23C16/50 , C23C16/455 , C23F1/00 , H01J37/32
CPC分类号： H01J37/32633 , C23C16/45536 , C23C16/45587 , C23C16/45589 , C23C16/50 , C23F1/00 , F04F9/00 , H01J37/32834 , H01J2237/18 , H01J2237/1825
摘要： A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.
摘要翻译：真空阱，使用真空阱的等离子体蚀刻系统和清洁真空阱的方法。真空阱包括挡板壳体; 以及设置在所述挡板壳体中的可移除的挡板组件，所述挡板组件包括一组挡板，所述挡板沿着支撑杆从第一挡板平板到最后的挡板间隔开，所述挡板交替地设置在所述支撑件的上方和下方并且交替地设置在挡板壳体的上部区域和下部区域中。

5. 发明授权

US4490193A Method for making diffusions into a substrate and electrical connections thereto using rare earth boride materials 失效
标题翻译：使用稀土硼化物材料制造扩散到基板和与其连接的方法
公开(公告)号：US4490193A
公开(公告)日：1984-12-25
申请号：US537128
申请日：1983-09-29
申请人： Mousa H. Ishaq , Stanley Roberts , James G. Ryan
发明人： Mousa H. Ishaq , Stanley Roberts , James G. Ryan
IPC分类号： H01L21/28 , H01L21/225 , H01L21/285
CPC分类号： H01L21/2254 , H01L21/28512
摘要： A method for diffusing a conductively determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a layer of a rare earth boride material over a predetermined surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the boride material to diffuse into the adjoining portion of the substrate to modify its conductive characteristics. At the same time a good electrical ohmic contact is established between the boride material and the adjoining substrate portion while the boride material retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.
摘要翻译：一种通过在衬底的预定表面部分上沉积稀土硼化物材料层并将衬底加热预定时间段来扩散半导体衬底中的导电性杂质并使其电接触的方法，足以使硼从硼化物材料扩散到衬底的相邻部分中以改变其导电特性。同时在硼化物材料和相邻的基底部分之间建立良好的电欧姆接触，同时硼化物材料即使在热处理过程中其一些硼的一部分向外扩散到衬底中之后也保持其导电性。

6. 发明授权

US06670283B2 Backside protection films 失效
标题翻译：背面保护膜
公开(公告)号：US06670283B2
公开(公告)日：2003-12-30
申请号：US09989389
申请日：2001-11-20
申请人： Faye D. Baker , Casey J. Grant , Mousa H. Ishaq , Joel M. Sharrow , James D. Weil
发明人： Faye D. Baker , Casey J. Grant , Mousa H. Ishaq , Joel M. Sharrow , James D. Weil
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02115 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612
摘要： Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.
摘要翻译：公开了一种制造半导体器件的方法，包括：（a）提供裸半导体衬底，所述衬底具有前侧和后侧; （b）在衬底的背面形成一个或多个保护膜; 和（c）执行一个或多个晶片制造步骤。可以去除一些或全部保护膜，并且在制造半导体器件期间该方法重复多次。

7. 发明授权

US4609429A Process for making a small dynamic memory cell structure 失效
标题翻译：制作小动态存储单元结构的过程
公开(公告)号：US4609429A
公开(公告)日：1986-09-02
申请号：US627250
申请日：1984-07-02
申请人： Mousa H. Ishaq , Wendell P. Noble, Jr.
发明人： Mousa H. Ishaq , Wendell P. Noble, Jr.
IPC分类号： H01L27/10 , H01L21/265 , H01L21/3213 , H01L21/8242 , H01L27/108 , H01L21/302
CPC分类号： H01L27/10844 , H01L21/2652 , H01L21/32136 , H01L21/32137
摘要： A process is provided for making a conductive structure for a semiconductor circuit, such as a one device dynamic random access memory cell, which includes the steps of depositing a conductive layer on a surface of a semiconductor substrate having a given type conductivity spaced from a storage node, depositing a layer of polysilicon over the conductive layer, depositing a layer of photoresist over the polysilicon layer, defining an opening in the photoresist layer and implanting ions of a conductivity type opposite to that of the given type conductivity through the opening and the polysilicon layer into the semiconductor substrate to form therein a conductive pocket or region having the opposite type conductivity resulting in, e.g., a highly conductive bit/sense line of a memory cell.
摘要翻译：提供了一种用于制造诸如一个器件动态随机存取存储器单元的半导体电路的导电结构的工艺，其包括以下步骤：在具有与储存器间隔开的给定类型电导率的半导体衬底的表面上沉积导电层在所述导电层上沉积多晶硅层，在所述多晶硅层上沉积一层光致抗蚀剂，在所述光致抗蚀剂层中限定开口并且通过所述开口和所述多晶硅注入与所述类型导电性相反的导电类型的离子层形成半导体衬底以在其中形成具有相反类型导电性的导电袋或区域，导致例如存储器单元的高导电位/感测线。

8. 发明授权

US07294554B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07294554B2
公开(公告)日：2007-11-13
申请号：US11276024
申请日：2006-02-10
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷污染。

9. 发明授权

US4432035A Method of making high dielectric constant insulators and capacitors using same 失效
标题翻译：制造高介电常数绝缘体和使用其的电容器的方法
公开(公告)号：US4432035A
公开(公告)日：1984-02-14
申请号：US387315
申请日：1982-06-11
申请人： Ning Hsieh , Eugene A. Irene , Mousa H. Ishaq , Stanley Roberts
发明人： Ning Hsieh , Eugene A. Irene , Mousa H. Ishaq , Stanley Roberts
IPC分类号： C01B33/12 , B05D5/12 , C01B33/113 , H01B3/02 , H01G2/12 , H01G4/06 , H01G4/08 , H01G4/10 , H01L21/314 , H01L21/316 , H01L21/822 , H01L27/04 , H01L29/94
CPC分类号： H01G2/12
摘要： An improved method of fabricating a stable high dielectric constant and low leakage dielectric material includes oxidizing at a temperature of about 400.degree. C. or higher a layer of a transition metal-silicon alloy having 40% to 90% transition metal by atomic weight to produce a silicate or homogeneous mixture. The mixture includes an oxide of the transition metal and silicon dioxide. The alloy may be deposited on, e.g., a semiconductor or an electrically conductive layer that is oxidation resistant, and the thickness of the mixture or oxidized alloy should be within the range of 5 to 50 nanometers. By depositing an electrically conductive layer on the homogeneous mixture, a capacitor having a high dielectric, low leakage dielectric medium is provided.
摘要翻译：制造稳定的高介电常数和低泄漏介电材料的改进方法包括在约400℃或更高的温度下氧化具有40％至90％过渡金属的过渡金属 - 硅合金的原子量以产生硅酸盐或均质混合物。该混合物包括过渡金属和二氧化硅的氧化物。合金可以沉积在例如耐氧化的半导体或导电层上，并且混合物或氧化合金的厚度应在5至50纳米的范围内。通过在均匀混合物上沉积导电层，提供具有高电介质，低漏电介质的电容器。

10. 发明授权

US07521748B2 Method to eliminate arsenic contamination in trench capacitors 失效
标题翻译：消除沟槽电容器中砷污染的方法
公开(公告)号：US07521748B2
公开(公告)日：2009-04-21
申请号：US11875503
申请日：2007-10-19
申请人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
发明人： Marshall J. Fleming, Jr. , Mousa H. Ishaq , Steven M. Shank , Michael C. Triplett
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷的污染。

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