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1. 发明授权

US07023444B2 Multi-texturing by walking an appropriately-sized supertile over a primitive 有权
标题翻译：通过在原始图像上行走适当尺寸的超重物进行多纹理化
公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译：渲染单元定位一个supertile，以便它与一个原语相交。渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。

2. 发明授权

US06803916B2 Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权
标题翻译：使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率
公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
CPC分类号： G06T15/00 , G06T11/40
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译：公开了一种用于光栅化和渲染图形数据的系统和方法。顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。

3. 发明授权

US07737994B1 Large-kernel convolution using multiple industry-standard graphics accelerators 有权
标题翻译：使用多个行业标准图形加速器的大内核卷积
公开(公告)号：US07737994B1
公开(公告)日：2010-06-15
申请号：US10673088
申请日：2003-09-26
申请人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
发明人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
IPC分类号： G06F15/80 , G09G5/00 , G06K9/64
CPC分类号： G06T11/40 , G06T1/20 , G09G5/14 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.
摘要翻译：公开了利用多个图形管线来执行大的内核卷积的多芯片系统和方法。每个图形流水线包括标准渲染单元和视频数据卷积单元。每个视频数据卷积单元从标准渲染单元的视频输出接收视频像素数据。视频数据卷积单元连接在一起。链中的每一组一个或多个视频数据卷积单元卷积由该组接收的视频像素数据。链中的最后一个视频数据卷积单元输出一个卷积像素流。

4. 发明授权

US06833834B2 Frame buffer organization and reordering 有权
标题翻译：帧缓冲区组织和重新排序
公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译：图形系统包括帧缓冲器，写地址生成器和像素缓冲器。从帧缓冲器接收到的像素突发可能不是显示顺序。在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。写入地址对应于每个相应像素的突发内的相对显示顺序。突发中的每个像素被存储到像素缓冲器中的其写入地址。这样，突发中的像素以像素缓冲器内的显示顺序存储。

5. 发明授权

US06795080B2 Batch processing of primitives for use with a texture accumulation buffer 有权
标题翻译：用于与纹理累加缓冲区一起使用的原语的批处理
公开(公告)号：US06795080B2
公开(公告)日：2004-09-21
申请号：US10060954
申请日：2002-01-30
申请人： Michael G. Lavelle , David C. Kehlet , Michael A. Wasserman , Nandini Ramani , Ranjit S. Oberoi
发明人： Michael G. Lavelle , David C. Kehlet , Michael A. Wasserman , Nandini Ramani , Ranjit S. Oberoi
IPC分类号： G06T1140
CPC分类号： G06T11/001
摘要： A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.
摘要翻译：图形系统被配置为将多层纹理信息应用于批量的图元。图形系统将基元收集到共享要应用的一组公共纹理图层的批次中。批量被限制，使得批次的总估计大小小于或等于纹理累积缓冲器的存储容量。图形系统将相应于批量原语的样本（或片段）存储在连续纹理层的应用之间的纹理累积缓冲器中。

6. 发明授权

US06914610B2 Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权
标题翻译：用于纹理累积缓冲区的图形原始尺寸估计和细分
公开(公告)号：US06914610B2
公开(公告)日：2005-07-05
申请号：US09861192
申请日：2001-05-18
申请人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
发明人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
IPC分类号： G06T15/04 , G09G5/36 , G09G5/00
CPC分类号： G06T11/40 , G06T15/04 , G09G5/363
摘要： A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.
摘要翻译：图形系统被配置为将多层纹理信息应用于原语。图形系统接收定义原语的参数，并对原语进行大小测试。如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量，则将原语划分为子标识符，并且图形系统将多层纹理应用于与原始。当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时，图形系统将从当前图层切换到该图层。图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。

7. 发明授权

US06731300B2 Efficient anti-aliased dot rasterization 有权
标题翻译：高效的抗锯齿点光栅化
公开(公告)号：US06731300B2
公开(公告)日：2004-05-04
申请号：US09861177
申请日：2001-05-18
申请人： Nandini Ramani , Michael A. Wasserman , Michael G. Lavelle , Mark E. Pascual , Kevin Tang , Daniel M. Chao
发明人： Nandini Ramani , Michael A. Wasserman , Michael G. Lavelle , Mark E. Pascual , Kevin Tang , Daniel M. Chao
IPC分类号： G06T1500
CPC分类号： G09G5/363 , G06T11/40 , G06T15/00 , G06T2200/12
摘要： A graphics system may be configured to render anti-aliased dots in terms of samples and to generate pixels by filtering the samples. The pixels are supplied to one or more display devices. The means used to generate the samples may perform the computation of radial distance at positions on a grid in a rendering coordinate space, and interpolate estimates for the radial distances of samples around the dot as needed based on the radii at the grid positions.
摘要翻译：图形系统可以被配置为在样本方面呈现抗锯齿点，并且通过对样本进行滤波来生成像素。像素被提供给一个或多个显示设备。用于生成样本的手段可以在渲染坐标空间中的网格上的位置处执行径向距离的计算，并且根据需要根据网格位置处的半径内插点周围的样本的径向距离的估计。

8. 发明授权

US06943797B2 Early primitive assembly and screen-space culling for multiple chip graphics system 有权
标题翻译：早期的原始装配和屏幕空间剔除多芯片图形系统
公开(公告)号：US06943797B2
公开(公告)日：2005-09-13
申请号：US10611271
申请日：2003-06-30
申请人： Michael A. Wasserman , Ewa M. Kubalska , Brian D. Emberling
发明人： Michael A. Wasserman , Ewa M. Kubalska , Brian D. Emberling
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00
CPC分类号： G06T15/005 , G06T1/60 , H04N19/42 , H04N19/80
摘要： A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
摘要翻译：公开了一种用于将原始汇编器并入一个或多个几何码片和一个或多个光栅化码片的每一个中的多芯片系统和方法。该系统可以允许在几何芯片中执行每个原始操作，并且还允许使用顶点数据接口将顶点数据发送到光栅化芯片。几何芯片中的原始汇编器可以将顶点组装成用于剪切测试的基元。几何芯片还可以针对一组屏幕空间区域的投影边界来测试组合的图元，其中每个区域被分配给光栅化芯片中的一个。驻留在多个区域中的这些原语可以被细分为两个或更多个新的基元，使得每个新的基元仅驻留在一个屏幕空间区域。然后，几何芯片可以将每个基元的顶点数据发送到相应的光栅化芯片。

9. 发明授权

US06670959B2 Method and apparatus for reducing inefficiencies in shared memory devices 有权
标题翻译：用于降低共享存储器件中的低效率的方法和装置
公开(公告)号：US06670959B2
公开(公告)日：2003-12-30
申请号：US09861481
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Glenn Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Glenn Gracon
IPC分类号： G06F1318
CPC分类号： G09G5/001 , G06F3/1431 , G06F13/1605 , G09G3/003 , G09G5/006 , G09G5/346 , G09G5/393 , G09G5/395 , G09G2360/128 , G09G2360/18
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.
摘要翻译：可以在多个显示通道之间共享的图形系统包括帧缓冲器，仲裁器和两个像素输出缓冲器。仲裁者在显示通道对帧缓冲器的显示信息请求之间进行仲裁，并将所选择的请求转发到帧缓冲器。帧缓冲器被分成第一和第二部分。仲裁器交替显示帧缓冲器的第一和第二部分之间的数据的信道请求。帧缓冲器响应于接收转发的请求而输出显示信息，并且与该显示信息相对应的像素被存储在输出缓冲器中。仲裁器根据每个请求显示通道的相关状态选择哪个请求转发到帧缓冲器。

10. 发明授权

US06654021B2 Multi-channel, demand-driven display controller 有权
公开(公告)号：US06654021B2
公开(公告)日：2003-11-25
申请号：US09861461
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
IPC分类号： G06F1318
CPC分类号： G09G5/12 , G06F3/1431 , G09G5/395 , G09G2360/123
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

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