专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07023444B2 Multi-texturing by walking an appropriately-sized supertile over a primitive 有权
标题翻译：通过在原始图像上行走适当尺寸的超重物进行多纹理化
公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译：渲染单元定位一个supertile，以便它与一个原语相交。渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。

2. 发明授权

US06924820B2 Over-evaluating samples during rasterization for improved datapath utilization 有权
标题翻译：在光栅化期间对样本进行过度评估，以提高数据路径利用率
公开(公告)号：US06924820B2
公开(公告)日：2005-08-02
申请号：US09962995
申请日：2001-09-25
申请人： Nandini Ramani , David C. Kehlet , Michael G. Lavelle , Mark E. Pascual , Ewa M. Kubalska , Yi-Ming Tian
发明人： Nandini Ramani , David C. Kehlet , Michael G. Lavelle , Mark E. Pascual , Ewa M. Kubalska , Yi-Ming Tian
IPC分类号： G06T11/40 , G09G5/00
CPC分类号： G06T11/40
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. To overcome fragmentation problems, the system's sample evaluation hardware may be configured to over-evaluate samples each clock cycle. Since a number of the samples will typically not survive evaluation because they will be outside the primitive being rendered, the remaining surviving samples may be combined into sets, with one set being forwarded to subsequent pipeline stages each clock cycle in order to attempt to keep the pipeline utilization high.
摘要翻译：公开了一种用于光栅化和渲染图形数据的系统和方法。顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。为了克服分裂问题，系统的样本评估硬件可能被配置为对每个时钟周期的样本进行过度评估。由于许多样本通常不能存活，因为它们将不在渲染原始图像之外，剩余的存活样本可以组合成集合，其中一个集合被转发到每个时钟周期的后续流水线阶段，以便尝试保持管道利用率高。

3. 发明授权

US06803916B2 Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权
标题翻译：使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率
公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
CPC分类号： G06T15/00 , G06T11/40
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译：公开了一种用于光栅化和渲染图形数据的系统和方法。顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。

4. 发明授权

US07737994B1 Large-kernel convolution using multiple industry-standard graphics accelerators 有权
标题翻译：使用多个行业标准图形加速器的大内核卷积
公开(公告)号：US07737994B1
公开(公告)日：2010-06-15
申请号：US10673088
申请日：2003-09-26
申请人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
发明人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
IPC分类号： G06F15/80 , G09G5/00 , G06K9/64
CPC分类号： G06T11/40 , G06T1/20 , G09G5/14 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.
摘要翻译：公开了利用多个图形管线来执行大的内核卷积的多芯片系统和方法。每个图形流水线包括标准渲染单元和视频数据卷积单元。每个视频数据卷积单元从标准渲染单元的视频输出接收视频像素数据。视频数据卷积单元连接在一起。链中的每一组一个或多个视频数据卷积单元卷积由该组接收的视频像素数据。链中的最后一个视频数据卷积单元输出一个卷积像素流。

5. 发明授权

US06833834B2 Frame buffer organization and reordering 有权
标题翻译：帧缓冲区组织和重新排序
公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Yan Yan Tang , Ewa M. Kubalska
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译：图形系统包括帧缓冲器，写地址生成器和像素缓冲器。从帧缓冲器接收到的像素突发可能不是显示顺序。在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。写入地址对应于每个相应像素的突发内的相对显示顺序。突发中的每个像素被存储到像素缓冲器中的其写入地址。这样，突发中的像素以像素缓冲器内的显示顺序存储。

6. 发明授权

US06859209B2 Graphics data accumulation for improved multi-layer texture performance 有权
标题翻译：用于改善多层纹理性能的图形数据累积
公开(公告)号：US06859209B2
公开(公告)日：2005-02-22
申请号：US09861468
申请日：2001-05-18
申请人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
发明人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
IPC分类号： G06T15/00 , G09G5/36 , G09G5/00
CPC分类号： G09G5/363 , G06T11/40 , G06T15/005
摘要： A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.
摘要翻译：图形系统将多层纹理信息应用于三角形。图形系统包括硬件加速器，帧缓冲器和视频输出处理器。硬件加速器接收三角形的顶点，识别与三角形相交的采样空间的片段，并将多层纹理应用于相交片段。多层纹理可以存储在硬件加速器外部的纹理存储器中。硬件加速器在将当前层的纹理应用于三角形的所有片段之后切换到下一个纹理层。硬件加速器包括（或耦合到）纹理累积缓冲器，其存储与连续纹理层的应用之间的三角形片段相关联的颜色值。帧缓冲器通过过滤存储从样本产生的样本和像素。视频输出处理器将像素转换为视频信号。

7. 发明授权

US06943797B2 Early primitive assembly and screen-space culling for multiple chip graphics system 有权
标题翻译：早期的原始装配和屏幕空间剔除多芯片图形系统
公开(公告)号：US06943797B2
公开(公告)日：2005-09-13
申请号：US10611271
申请日：2003-06-30
申请人： Michael A. Wasserman , Ewa M. Kubalska , Brian D. Emberling
发明人： Michael A. Wasserman , Ewa M. Kubalska , Brian D. Emberling
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00
CPC分类号： G06T15/005 , G06T1/60 , H04N19/42 , H04N19/80
摘要： A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
摘要翻译：公开了一种用于将原始汇编器并入一个或多个几何码片和一个或多个光栅化码片的每一个中的多芯片系统和方法。该系统可以允许在几何芯片中执行每个原始操作，并且还允许使用顶点数据接口将顶点数据发送到光栅化芯片。几何芯片中的原始汇编器可以将顶点组装成用于剪切测试的基元。几何芯片还可以针对一组屏幕空间区域的投影边界来测试组合的图元，其中每个区域被分配给光栅化芯片中的一个。驻留在多个区域中的这些原语可以被细分为两个或更多个新的基元，使得每个新的基元仅驻留在一个屏幕空间区域。然后，几何芯片可以将每个基元的顶点数据发送到相应的光栅化芯片。

8. 发明授权

US06781406B2 Using observability logic for real-time debugging of ASICs 有权
标题翻译：使用可观察性逻辑来实现ASIC的实时调试
公开(公告)号：US06781406B2
公开(公告)日：2004-08-24
申请号：US10090481
申请日：2002-03-04
申请人： Brian D. Emberling , Ewa M. Kubalska
发明人： Brian D. Emberling , Ewa M. Kubalska
IPC分类号： H03K19173
CPC分类号： G01R31/318516 , G01R31/31705 , G01R31/3172 , G01R31/31722 , G01R31/31723
摘要： An integrated circuit including logic for testing internal operation of the integrated circuit. The integrated circuit may comprise a plurality of internal functional blocks coupled by a plurality of internal buses. The integrated circuit may also comprise a set of test control input pins and a set of test output pins comprised on the integrated circuit. The integrated circuit may comprise selection logic. The selection logic comprises inputs coupled to various ones of the internal buses, an output coupled to the set of test output pins, and a select input coupled to receive select signals from the set of test control input pins. The selection logic is operable to select internal bus signals from an internal bus based on the select signals from the test control input pins, and the selection logic is configured to output the selected internal bus signals to the set of test output pins. The integrated circuit thus allows multiplexing of different critical internal buses so that the signals on the critical buses may be output for observation via selected test pins on the integrated circuit. The observability logic may be configured to switch slowly relative to the internal busses, and the generation of the observability logic and testing may be automated.
摘要翻译：一种集成电路，包括用于测试集成电路的内部操作的逻辑。集成电路可以包括通过多个内部总线耦合的多个内部功能块。集成电路还可以包括一组测试控制输入引脚和一组包含在集成电路上的测试输出引脚。集成电路可以包括选择逻辑。选择逻辑包括耦合到各种内部总线的输入，耦合到该组测试输出引脚的输出以及耦合以从该组测试控制输入引脚接收选择信号的选择输入。选择逻辑可操作以基于来自测试控制输入引脚的选择信号从内部总线选择内部总线信号，并且选择逻辑被配置为将所选择的内部总线信号输出到测试输出引脚组。因此，集成电路允许复用不同的关键内部总线，使得可以输出关键总线上的信号，以便通过集成电路上的选定测试引脚进行观察。可观测性逻辑可以被配置为相对于内部总线缓慢地切换，并且可观察性逻辑和测试的产生可以是自动化的。

9. 发明授权

US06842851B2 Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay 有权
标题翻译：在一段时间延迟结束时，以一系列计算单元读取形成处理流水线的选定寄存器
公开(公告)号：US06842851B2
公开(公告)日：2005-01-11
申请号：US10085642
申请日：2002-02-28
申请人： Wayne Eric Burk , Ewa M. Kubalska , Brian D. Emberling
发明人： Wayne Eric Burk , Ewa M. Kubalska , Brian D. Emberling
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3863 , G06F9/30101 , G06F9/3867 , G06F9/3869 , G06F9/3897
摘要： A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.
摘要翻译：一种用于从具有多个计算单元的计算流水线读取寄存器内容的系统和方法。该系统包括回读总线和读取控制单元。回读总线具有串联耦合的多个逻辑单元。每个逻辑单元耦合到相应的一个计算单元。读取控制单元通过对应的负载线耦合到每个计算单元，并且被配置为响应于寄存器读取请求而在其中一个负载线上断言负载信号。每个计算单元被配置为响应于检测到其相应负载线上的负载信号的断言而将数据值从所选择的寄存器发送到回读总线。

10. 发明授权

US06731292B2 System and method for controlling a number of outstanding data transactions within an integrated circuit 有权
标题翻译：用于控制集成电路内的许多未完成数据事务的系统和方法
公开(公告)号：US06731292B2
公开(公告)日：2004-05-04
申请号：US10092016
申请日：2002-03-06
申请人： Wayne Eric Burk , Ewa M. Kubalska , Brian D. Emberling
发明人： Wayne Eric Burk , Ewa M. Kubalska , Brian D. Emberling
IPC分类号： G06F1576
CPC分类号： G09G5/395 , G06F13/405 , G06T1/20
摘要： An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.
摘要翻译：集成电路可以包括若干组件，一个或多个接口，互连（例如，总线）和控制器。每个组件可以被配置为断言读取请求以读取外部存储到集成电路的数据。接口可以被配置为输出由其中一个组件确定的读取请求并响应于输出请求而接收数据。互连可以被耦合以执行一个或多个数据事务以将数据从一个接口传送到一个或多个组件。响应于由其中一个组件所声明的读取请求，控制器可以根据未完成数据事务的总数与最大允许数量的未完成数据事务的比较来禁止由读取请求发起的读取事务的执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式