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1. 发明授权

US06603329B1 Systems and methods for on-chip impedance termination 有权
标题翻译：用于片上阻抗终止的系统和方法
公开(公告)号：US06603329B1
公开(公告)日：2003-08-05
申请号：US10044459
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278 , H04L25/0298
摘要： Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.
摘要翻译：提供用于片上阻抗终止的技术，其大大减少了需要在多对差分输入/输出（I / O）引脚上提供阻抗终端的外部电阻器的数量。本发明的片上阻抗终端电路可以包括放大器，反馈回路和阻抗终端电路。将参考电压提供给放大器的第一输入端。反馈回路耦合在放大器的输出端和放大器的第二输入端之间。放大器驱动其输出电压，使得第二输入端子处的电压与第一输入端子处的电压匹配。放大器的输出电压决定了阻抗终端电路的电阻。阻抗端接电路耦合在差分I / O引脚之间。

2. 发明授权

US06384629B2 High-speed programmable interconnect 有权
标题翻译：高速可编程互连
公开(公告)号：US06384629B2
公开(公告)日：2002-05-07
申请号：US09738403
申请日：2000-12-15
申请人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
发明人： Joseph Huang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , Xiaobao Wang , Richard G. Cliff
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , G01R31/318555 , G06F11/2273 , H03K19/17792
摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.
摘要翻译：水平导体与逻辑元件输入之间的互连改善。在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。这允许更快的切换操作。提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

3. 发明授权

US08531205B1 Programmable output buffer 有权
标题翻译：可编程输出缓冲器
公开(公告)号：US08531205B1
公开(公告)日：2013-09-10
申请号：US13363108
申请日：2012-01-31
申请人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
发明人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/018585 , H03K19/17744 , H03K19/17788
摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚驱动电路。第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。还公开了其它实施例和特征。

4. 发明授权

US07358783B1 Voltage, temperature, and process independent programmable phase shift for PLL 有权
标题翻译： PLL的电压，温度和过程独立的可编程相移
公开(公告)号：US07358783B1
公开(公告)日：2008-04-15
申请号：US10400191
申请日：2003-03-25
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
IPC分类号： H03L7/095
CPC分类号： H03L7/0891 , H03F1/301 , H03H11/245 , H03K19/1774 , H03K23/665 , H03K2005/00045 , H03L7/081 , H03L7/089 , H03L7/0996 , H03L7/0997 , H03L7/18 , H03L7/183
摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.
摘要翻译：电路提供可编程相移特征，其中相移可由用户可编程地选择。该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。在实现中，使用两个可编程计数器来实现可编程相移电路。

5. 发明授权

US07205788B1 Programmable on-chip differential termination impedance 有权
标题翻译：可编程片上差分终端阻抗
公开(公告)号：US07205788B1
公开(公告)日：2007-04-17
申请号：US11086979
申请日：2005-03-21
申请人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
发明人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/003
CPC分类号： H04L25/0278
摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.
摘要翻译：电路和方法用于集成电路上的阻抗终端。在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。晶体管耦合在终端电阻网络中。晶体管为差分IO引脚提供额外的终端阻抗。晶体管可以单独打开或关闭，以改变阻抗终止。

6. 发明授权

US06888369B1 Programmable on-chip differential termination impedance 有权
标题翻译：可编程片上差分终端阻抗
公开(公告)号：US06888369B1
公开(公告)日：2005-05-03
申请号：US10622314
申请日：2003-07-17
申请人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
发明人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/003 , H04L25/02
CPC分类号： H04L25/0278
摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.
摘要翻译：电路和方法用于集成电路上的阻抗终端。在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。晶体管耦合在终端电阻网络中。晶体管为差分IO引脚提供额外的终端阻抗。晶体管可以单独打开或关闭，以改变阻抗终止。

7. 发明授权

US06798237B1 On-chip impedance matching circuit 有权
标题翻译：片内阻抗匹配电路
公开(公告)号：US06798237B1
公开(公告)日：2004-09-28
申请号：US10044365
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278
摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.
摘要翻译：提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

8. 发明授权

US06335636B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
公开(公告)号：US06335636B1
公开(公告)日：2002-01-01
申请号：US09846409
申请日：2001-05-01
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

9. 发明授权

US06236231B1 Programmable logic integrated circuit devices with low voltage differential signaling capabilities 有权
标题翻译：具有低电压差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06236231B1
公开(公告)日：2001-05-22
申请号：US09340222
申请日：1999-06-25
申请人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
发明人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.
摘要翻译：可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

10. 发明授权

US09099999B1 Adjustable drive strength input-output buffer circuitry 有权
标题翻译：可调驱动强度输入输出缓冲电路
公开(公告)号：US09099999B1
公开(公告)日：2015-08-04
申请号：US13485768
申请日：2012-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
IPC分类号： H01L29/73 , H01L29/40 , H03K17/00 , H05K1/18 , H01L25/065 , H01L27/06
CPC分类号： H03K17/00 , H01L25/0652 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/144 , H05K1/181 , H05K2201/045 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.
摘要翻译：提供了一种多芯片封装中的集成电路。该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。

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