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1. 发明授权

US07710149B1 Input buffer for multiple differential I/O standards 失效
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07710149B1
公开(公告)日：2010-05-04
申请号：US12190530
申请日：2008-08-12
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

2. 发明授权

US07425844B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07425844B1
公开(公告)日：2008-09-16
申请号：US11697299
申请日：2007-04-06
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

3. 发明授权

US06992947B1 Dual-port SRAM in a programmable logic device 失效
公开(公告)号：US06992947B1
公开(公告)日：2006-01-31
申请号：US10696209
申请日：2003-10-28
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

4. 发明授权

US06911860B1 On/off reference voltage switch for multiple I/O standards 有权
标题翻译：用于多个I / O标准的开/关参考电压开关
公开(公告)号：US06911860B1
公开(公告)日：2005-06-28
申请号：US10037716
申请日：2001-11-09
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
IPC分类号： H03K17/35
CPC分类号： H03K17/6871 , H03K3/356113 , H03K17/063
摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.
摘要翻译：开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。该电路接收与设备的I / O电源不同的专用电源。其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

5. 发明授权

US06731142B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06731142B1
公开(公告)日：2004-05-04
申请号：US10412705
申请日：2003-04-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

6. 发明授权

US06731137B1 Programmable, staged, bus hold and weak pull-up for bi-directional I/O 有权
标题翻译：可编程，分段，总线保持和弱上拉双向I / O
公开(公告)号：US06731137B1
公开(公告)日：2004-05-04
申请号：US10131976
申请日：2002-04-24
申请人： Gopinath Rangan , Chiakang Sung , Xiaobao Wang , Philip Pan , Yan Chong , In Whan Kim , Khai Nguyen , Bonnie Wang , Tzung-Chin Chang , Joseph Huang
发明人： Gopinath Rangan , Chiakang Sung , Xiaobao Wang , Philip Pan , Yan Chong , In Whan Kim , Khai Nguyen , Bonnie Wang , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K3356
CPC分类号： H04L25/0264 , H03K5/08
摘要： The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up circuit is directly coupled to the resistor at the first node. The bus hold circuit is coupled to the resistor at the second node.
摘要翻译：本发明包括总线保持和弱上拉电路。具有第一节点和第二节点的电阻器耦合到第一节点处的双向I / O引脚。弱上拉电路直接耦合到第一节点处的电阻器。总线保持电路耦合到第二节点处的电阻器。

7. 发明授权

US06549045B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06549045B1
公开(公告)日：2003-04-15
申请号：US10043620
申请日：2002-01-11
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

8. 发明授权

US06535031B1 Programmable logic integrated circuit devices with low voltage differential signaling capabilities 有权
公开(公告)号：US06535031B1
公开(公告)日：2003-03-18
申请号：US10146438
申请日：2002-05-13
申请人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G Cliff , Joseph Huang , Bonnie I Wang , Wayne Yeung
发明人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G Cliff , Joseph Huang , Bonnie I Wang , Wayne Yeung
IPC分类号： H03K522
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

9. 发明授权

US06246270B1 Innovated AC kicker for high speed low voltage swing differential output buffer with temperature compensation 有权
标题翻译：用于具有温度补偿功能的高速低电压摆幅差分输出缓冲器的创新交流踢枪
公开(公告)号：US06246270B1
公开(公告)日：2001-06-12
申请号：US09345434
申请日：1999-07-01
申请人： Bonnie Wang , Joseph Huang , Wayne Yeung , Chiakang Sung , Richard Cliff , Khai Nguyen , Xiaobao Wang , In Whan Kim
发明人： Bonnie Wang , Joseph Huang , Wayne Yeung , Chiakang Sung , Richard Cliff , Khai Nguyen , Xiaobao Wang , In Whan Kim
IPC分类号： H03K426
CPC分类号： H03K17/04206 , H03K17/6871
摘要： Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.
摘要翻译：公开了用于可编程逻辑控制或其他集成电路的输出放大器的电流增压器或激光器。电流增压器包括控制机构和辅助电压源。当启动输出状态的变化时，控制机构将辅助电源连接到输出放大器的输出端。在完成输出状态改变后，控制机构将输出放大器的输出端的辅助电源断开。以这种方式，输出放大器可以以相对较高的转换速率驱动较高的电容负载。

10. 发明授权

US07358783B1 Voltage, temperature, and process independent programmable phase shift for PLL 有权
标题翻译： PLL的电压，温度和过程独立的可编程相移
公开(公告)号：US07358783B1
公开(公告)日：2008-04-15
申请号：US10400191
申请日：2003-03-25
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
IPC分类号： H03L7/095
CPC分类号： H03L7/0891 , H03F1/301 , H03H11/245 , H03K19/1774 , H03K23/665 , H03K2005/00045 , H03L7/081 , H03L7/089 , H03L7/0996 , H03L7/0997 , H03L7/18 , H03L7/183
摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.
摘要翻译：电路提供可编程相移特征，其中相移可由用户可编程地选择。该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。在实现中，使用两个可编程计数器来实现可编程相移电路。

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