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1. 发明授权

US06335636B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
公开(公告)号：US06335636B1
公开(公告)日：2002-01-01
申请号：US09846409
申请日：2001-05-01
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

2. 发明授权

US06346827B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
标题翻译：可编程逻辑器件输入/输出电路可配置为参考电压输入电路
公开(公告)号：US06346827B1
公开(公告)日：2002-02-12
申请号：US09366937
申请日：1999-08-04
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.
摘要翻译：可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。在标准I / O模式下，I / O缓冲区可以运行。参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

3. 发明授权

US06965251B1 Input buffer with hysteresis option 失效
标题翻译：具有滞后选项的输入缓冲器
公开(公告)号：US06965251B1
公开(公告)日：2005-11-15
申请号：US10708243
申请日：2004-02-18
申请人： Neil Nghia Tran , Nima Gilanpour , Myron W. Wong , Weiying Ding
发明人： Neil Nghia Tran , Nima Gilanpour , Myron W. Wong , Weiying Ding
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/018585
摘要： The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.
摘要翻译：本发明提供了可以在诸如输入缓冲器的集成电路的输入端使用的高速缓冲器。该缓冲器可以被配置为用作具有单个切换阈值的标准缓冲器，例如TTL至CMOS缓冲器，或者用作具有迟滞的施密特触发器，其作为至少两个切换阈值。集成电路可以是可编程逻辑器件（PLD）或现场可编程门阵列（FPGA），但是在其他实施例中，集成电路可以是其他类型的器件，例如微处理器，ASIC或存储器。

4. 发明授权

US06236237B1 Output buffer predriver with edge compensation 有权
标题翻译：输出缓冲器预驱动器，带边缘补偿
公开(公告)号：US06236237B1
公开(公告)日：2001-05-22
申请号：US09258165
申请日：1999-02-25
申请人： Myron W. Wong , Mark Chan
发明人： Myron W. Wong , Mark Chan
IPC分类号： H03K1901
CPC分类号： H03K19/0013
摘要： An output buffer with feedback to a predriver circuit such that the effective size of the predriver buffers are momentarily adjusted to favor a particular transition (i.e., low-to-high or high-to-low). The delayed output selectively alters the input threshold characteristic of the predriver circuit to favor the appropriate transition. Thus, the time during which the output drivers are subject to a crowbar current is reduced over previous devices.
摘要翻译：具有反馈给预驱动电路的输出缓冲器，使得暂时调整预驱动缓冲器的有效大小以有利于特定的转变（即从低到高或从高到低）。延迟输出选择性地改变预驱动电路的输入阈值特性以有利于适当的转换。因此，输出驱动器遭受撬棒电流的时间比以前的器件减少。

5. 发明授权

US6005379A Power compensating voltage reference 失效
标题翻译：功率补偿电压基准
公开(公告)号：US6005379A
公开(公告)日：1999-12-21
申请号：US80910
申请日：1998-05-18
申请人： Myron W. Wong , William Bradley Vest
发明人： Myron W. Wong , William Bradley Vest
IPC分类号： G05F3/24 , G11C5/14 , G05F3/16 , H03K3/01
CPC分类号： G11C5/147 , G05F3/242
摘要： A power supply independent voltage reference circuit is disclosed. According to the invention a reference voltage is generated at a common node between a pull-up transistor that is biased by a power supply dependent bias voltage, and a pull-down transistor that is biased by a feedback signal based on the output voltage level.
摘要翻译：公开了一种独立于电源的电压参考电路。根据本发明，在由依赖于电源的偏置电压偏置的上拉晶体管和基于输出电压电平的反馈信号偏置的下拉晶体管之间的公共节点处产生参考电压。

6. 发明授权

US5850365A Sense amplifier with individually optimized high and low power modes 失效
标题翻译：感应放大器，具有单独优化的高功率和低功耗模式
公开(公告)号：US5850365A
公开(公告)日：1998-12-15
申请号：US772567
申请日：1996-12-24
申请人： Dirk A. Reese , Myron W. Wong , John C. Costello
发明人： Dirk A. Reese , Myron W. Wong , John C. Costello
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C7/067
摘要： The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.
摘要翻译：本发明是一种与可编程逻辑器件一起使用的读出放大器电路，通过主动地限制其正在感测的位线上的电压摆幅而不是被动地感测电压来提供改进的开关时间，采用反馈电路来进一步提高开关时间，可以选择性地在低功率模式下操作而不显着降低开关速度。可以添加包括由参考电位供应的电位控制的可变电流限制器的电压参考控制电路，以提高抗噪声性能。设计参考电位的电路被设计成使得其对制造变化的敏感度基本上类似于读出放大器的灵敏度，并因此相应地调整参考电位。

7. 发明授权

US5767734A High-voltage pump with initiation scheme 失效
标题翻译：高压泵具有启动方案
公开(公告)号：US5767734A
公开(公告)日：1998-06-16
申请号：US576741
申请日：1995-12-21
申请人： William B. Vest , Myron W. Wong
发明人： William B. Vest , Myron W. Wong
IPC分类号： G11C5/14 , G11C16/30 , H03K17/06 , H03K17/10 , H03K17/687
CPC分类号： G11C16/30 , G11C5/145 , H03K17/063
摘要： A high voltage pump with an initiation scheme to achieve voltages above VDD. In response to a pulse signal, an initiation voltage is placed on a first node (515) of a voltage pump to initiate pumping action. The initiation voltage is passed through a transistor (545) coupled between a high voltage output node (415) and the first node (515) of the voltage pump. The first node (515) is coupled through a capacitor (510) to an oscillator (405) which charges the first node (515). A high voltage is produced at the high voltage output node (415). The initiation scheme may be applied to one-stage and multiple-stage voltage pumps.
摘要翻译：具有启动方案的高压泵，可实现高于VDD的电压。响应于脉冲信号，启动电压被放置在电压泵的第一节点（515）上以启动泵送动作。启动电压通过耦合在电压泵的高压输出节点（415）和第一节点（515）之间的晶体管（545）。第一节点（515）通过电容器（510）耦合到对第一节点（515）充电的振荡器（405）。在高电压输出节点（415）产生高电压。启动方案可以应用于一级和多级电压泵。

8. 发明授权

US5493526A Method and apparatus for enhanced EPROM and EEPROM programmability and process scaling 失效
标题翻译：用于增强EPROM和EEPROM可编程性和处理缩放的方法和装置
公开(公告)号：US5493526A
公开(公告)日：1996-02-20
申请号：US227500
申请日：1994-04-14
申请人： John E. Turner , Myron W. Wong
发明人： John E. Turner , Myron W. Wong
IPC分类号： G11C16/10 , G11C7/00
CPC分类号： G11C16/10
摘要： An EPROM or EEPROM employs an alternate voltage level of 2 volts replaces solid ground (0 volts) during programming and performs a `zero` logic level function. This `soft` zero of 2 volts is applied to bit lines not selected for programming. As a soft zero, this alternative voltage reduces internal voltage stresses and helps prevent field inversion and keep parasitic field transistors between bit lines shut off. By reducing internal voltage stresses on gate oxides, and by helping prevent field inversion, the use of a soft zero voltage allows smaller circuit architectures to be designed for a given high programming voltage.
摘要翻译：在编程期间，EPROM或EEPROM采用2伏的交替电压电平替代实心地（0伏），并执行“零”逻辑电平功能。这个2伏的“软”零点被施加到未被选择用于编程的位线。作为软零，这种替代电压降低内部电压应力，并有助于防止场反转，并保持位线之间的寄生场晶体管截止。通过减小栅极氧化物上的内部电压应力，并通过有助于防止场反转，使用软零电压可以为给定的高编程电压设计更小的电路架构。

9. 发明授权

US5369314A Programmable logic device with redundant circuitry 失效
标题翻译：具有冗余电路的可编程逻辑器件
公开(公告)号：US5369314A
公开(公告)日：1994-11-29
申请号：US199620
申请日：1994-02-22
申请人： Rakesh H. Patel , Myron W. Wong
发明人： Rakesh H. Patel , Myron W. Wong
IPC分类号： G06F11/20 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/00392
摘要： A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the programmable logic device. The programmable logic device is arranged in rows and columns of programmable logic containing logic array blocks, which a user selectively configures by loading programming data into vertical and horizontal programming blocks. Programming blocks are used to program the logic array blocks and various associated logic circuitry. When the redundant circuitry is switched into place, the programming data is redirected to the appropriate programming blocks, so that the device functions identically, regardless of whether or not the redundant circuitry is used.
摘要翻译：提供了一种具有冗余电路的可编程逻辑器件。当可编程逻辑器件电路的一部分被发现是有缺陷的时候，通过对可编程逻辑器件的电路的适当部分进行编程，将冗余电路切换到使用中来代替有缺陷的电路。可编程逻辑器件被布置成包含逻辑阵列块的可编程逻辑的行和列，用户通过将编程数据加载到垂直和水平编程块中来选择性地配置。编程块用于对逻辑阵列块和各种相关的逻辑电路进行编程。当冗余电路切换到位时，编程数据被重定向到相应的编程块，使得器件的功能相同，而不管冗余电路是否被使用。

10. 发明授权

US06646919B1 Apparatus and method for margin testing single polysilicon EEPROM cells 失效
标题翻译：单个多晶硅EEPROM单元的边缘测试的装置和方法
公开(公告)号：US06646919B1
公开(公告)日：2003-11-11
申请号：US09874716
申请日：2001-06-04
申请人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
发明人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译：公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除电池的裕度电压进入可测量范围。

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