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1. 发明授权

US08531205B1 Programmable output buffer 有权
标题翻译：可编程输出缓冲器
公开(公告)号：US08531205B1
公开(公告)日：2013-09-10
申请号：US13363108
申请日：2012-01-31
申请人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
发明人： Bonnie I. Wang , Chiakang Sung , Xiaobao Wang , Khai Nguyen , Joseph Huang
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/018585 , H03K19/17744 , H03K19/17788
摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚驱动电路。第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。还公开了其它实施例和特征。

2. 发明授权

US08098082B1 Multiple data rate interface architecture 有权
标题翻译：多数据速率接口架构
公开(公告)号：US08098082B1
公开(公告)日：2012-01-17
申请号：US12954204
申请日：2010-11-24
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

3. 发明授权

US07859304B1 Multiple data rate interface architecture 有权
标题翻译：多数据速率接口架构
公开(公告)号：US07859304B1
公开(公告)日：2010-12-28
申请号：US12329553
申请日：2008-12-06
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

4. 发明授权

US07358783B1 Voltage, temperature, and process independent programmable phase shift for PLL 有权
标题翻译： PLL的电压，温度和过程独立的可编程相移
公开(公告)号：US07358783B1
公开(公告)日：2008-04-15
申请号：US10400191
申请日：2003-03-25
申请人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
发明人： Bonnie I. Wang , Joseph Huang , Chiakang Sung , Xiaobao Wang , In Whan Kim , Wayne Yeung , Khai Nguyen
IPC分类号： H03L7/095
CPC分类号： H03L7/0891 , H03F1/301 , H03H11/245 , H03K19/1774 , H03K23/665 , H03K2005/00045 , H03L7/081 , H03L7/089 , H03L7/0996 , H03L7/0997 , H03L7/18 , H03L7/183
摘要： A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.
摘要翻译：电路提供可编程相移特征，其中相移可由用户可编程地选择。该电路可以并入可编程逻辑器件（PLD）或现场可编程门阵列（FPGA）中，以提供额外的可编程特性。可编程相移电路可以在锁相环（PLL）或延迟锁定环（DLL）电路内实现。在实现中，使用两个可编程计数器来实现可编程相移电路。

5. 发明授权

US07205788B1 Programmable on-chip differential termination impedance 有权
标题翻译：可编程片上差分终端阻抗
公开(公告)号：US07205788B1
公开(公告)日：2007-04-17
申请号：US11086979
申请日：2005-03-21
申请人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
发明人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/003
CPC分类号： H04L25/0278
摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.
摘要翻译：电路和方法用于集成电路上的阻抗终端。在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。晶体管耦合在终端电阻网络中。晶体管为差分IO引脚提供额外的终端阻抗。晶体管可以单独打开或关闭，以改变阻抗终止。

6. 发明授权

US07031222B1 DQS postamble filtering 失效
标题翻译： DQS后同步码过滤
公开(公告)号：US07031222B1
公开(公告)日：2006-04-18
申请号：US11046007
申请日：2005-01-28
申请人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
发明人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , H03M9/00
摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.
摘要翻译：用于在高速数据接口处过滤信号的电路，方法和装置。一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。时钟输入端口与输入单元连接或断开。当接收到数据脉冲串时，时钟输入端口连接到输入单元。当数据突发结束时，时钟输入端口与输入单元断开连接。在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。该信号随后改变指示正在接收最后一个数据位的状态。当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

7. 发明授权

US06888369B1 Programmable on-chip differential termination impedance 有权
标题翻译：可编程片上差分终端阻抗
公开(公告)号：US06888369B1
公开(公告)日：2005-05-03
申请号：US10622314
申请日：2003-07-17
申请人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
发明人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen
IPC分类号： H03K19/003 , H04L25/02
CPC分类号： H04L25/0278
摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.
摘要翻译：电路和方法用于集成电路上的阻抗终端。在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。晶体管耦合在终端电阻网络中。晶体管为差分IO引脚提供额外的终端阻抗。晶体管可以单独打开或关闭，以改变阻抗终止。

8. 发明授权

US06798237B1 On-chip impedance matching circuit 有权
标题翻译：片内阻抗匹配电路
公开(公告)号：US06798237B1
公开(公告)日：2004-09-28
申请号：US10044365
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278
摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.
摘要翻译：提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

9. 发明授权

US06335636B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
公开(公告)号：US06335636B1
公开(公告)日：2002-01-01
申请号：US09846409
申请日：2001-05-01
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , Im Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

10. 发明授权

US06252419B1 LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
标题翻译： LVDS接口结合了可编程逻辑器件中的锁相环电路
公开(公告)号：US06252419B1
公开(公告)日：2001-06-26
申请号：US09368464
申请日：1999-08-04
申请人： Chiakang Sung , Bonnie I. Wang , Richard G. Cliff
发明人： Chiakang Sung , Bonnie I. Wang , Richard G. Cliff
IPC分类号： H03K19173
CPC分类号： H03L7/18 , H03L7/07 , H03L7/0891
摘要： An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.
摘要翻译：用于可编程逻辑器件的LVDS接口使用锁相环（“PLL”）电路为数据输入和输出提供数据时钟。 PLL时钟是高精度的，每个包括一个乘以W的计数器，以便可以使用倍增和非乘法时钟。倍增时钟用于将数据串行时移到或移出移位寄存器链。非乘法时钟用于并行加载或读取移位寄存器链中的寄存器。从单个PLL提供相乘和非乘法时钟确保时钟处于正确的相位关系，以便串行输入或输出以及并行加载或卸载被正确同步。

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