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1. 发明授权

US07547603B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
标题翻译：具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
公开(公告)号：US07547603B2
公开(公告)日：2009-06-16
申请号：US11520993
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

2. 发明授权

US07129536B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
公开(公告)号：US07129536B2
公开(公告)日：2006-10-31
申请号：US10934246
申请日：2004-09-02
申请人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

3. 发明授权

US07537996B2 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate 有权
标题翻译：形成具有掩埋源极线和浮栅的浮栅存储器单元的半导体存储器阵列的自对准方法
公开(公告)号：US07537996B2
公开(公告)日：2009-05-26
申请号：US11166882
申请日：2005-06-24
申请人： Yaw Wen Hu , Sohrab Kianian
发明人： Yaw Wen Hu , Sohrab Kianian
IPC分类号： H01L21/8247
CPC分类号： H01L27/105 , H01L27/11553
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
摘要翻译：一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。

4. 发明授权

US06891220B2 Method of programming electrons onto a floating gate of a non-volatile memory cell 有权
标题翻译：将电子编程到非易失性存储单元的浮动栅极上的方法
公开(公告)号：US06891220B2
公开(公告)日：2005-05-10
申请号：US10757830
申请日：2004-01-13
申请人： Bing Yeh , Sohrab Kianian , Yaw Wen Hu
发明人： Bing Yeh , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/105 , H01L27/11553
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region. A method of programming the cell comprises the steps of creating an inversion layer in the second portion of the channel. A stream of electrons is generated at the drain region which is adjacent to the inversion layer, and the stream of electrons is passed through the inversion layer, reaching a pinch off point. The electrons are accelerated through the depletion region by the field lines from the floating gate, with little or no scattering, causing the electrons to be accelerated through the insulator, separating the floating gate from the substrate, and injected onto the floating gate.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。编程单元的方法包括在通道的第二部分中创建反转层的步骤。在与反转层相邻的漏极区域处产生电子流，并且电子流通过反转层，达到夹断点。电子通过来自浮置栅极的场线通过耗尽区加速，几乎没有散射或不散射，导致电子通过绝缘体加速，将浮动栅极与衬底分离，并注入浮栅。

5. 发明授权

US06952034B2 Semiconductor memory array of floating gate memory cells with buried source line and floating gate 有权
标题翻译：具有埋地源极线和浮栅的浮动存储单元的半导体存储器阵列
公开(公告)号：US06952034B2
公开(公告)日：2005-10-04
申请号：US10358623
申请日：2003-02-04
申请人： Yaw Wen Hu , Sohrab Kianian
发明人： Yaw Wen Hu , Sohrab Kianian
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11553
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
摘要翻译：一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。

6. 发明申请

US20090309182A1 ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE 审中-公开
标题翻译：静电放电保护结构
公开(公告)号：US20090309182A1
公开(公告)日：2009-12-17
申请号：US12140195
申请日：2008-06-16
申请人： Kung-Yen Su , Yaw Wen Hu , Bomy Chen , Kevin Gene-Wah Jew
发明人： Kung-Yen Su , Yaw Wen Hu , Bomy Chen , Kevin Gene-Wah Jew
IPC分类号： H01L23/62
CPC分类号： H01L27/0259
摘要： A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well. A third region of the first conductivity type, is immediately adjacent to and in contact with the second region, substantially beneath the second region. A fourth region of the first conductivity type is in the well, along the top surface thereof, and spaced apart from the first region. The first region and the fourth region receive the ESD signal.
摘要翻译：用于保护集成电路免受ESD信号的集成电路的静电放电（ESD）结构的第一实施例具有第一导电类型的衬底。衬底具有顶表面。第二导电类型的第一区域靠近顶表面并接收ESD信号。第二导电类型的第二区域在基板中，在基本上垂直的方向上与第一区域分离并间隔开。第一导电类型的第三区域，其浓度比衬底更重，与第二区域紧邻并与第二区域接触，基本上在第二区域下方。在第二实施例中，在第一导电类型的衬底中提供第二导电类型的阱。井有顶面。第二导电类型的第一区域靠近顶表面。第二导电类型的第二区域在井中，基本上沿着井的底部。第一导电类型的第三区域紧邻第二区域并与第二区域接触，基本上在第二区域下方。第一导电类型的第四区域沿着其顶表面位于阱中并与第一区域间隔开。第一区域和第四区域接收ESD信号。

7. 发明授权

US07119396B2 NROM device 有权
标题翻译： NROM设备
公开(公告)号：US07119396B2
公开(公告)日：2006-10-10
申请号：US10962008
申请日：2004-10-08
申请人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
发明人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.
摘要翻译：一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸，电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

8. 发明授权

US07868375B2 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

9. 发明申请

US20090201744A1 Method For Erasing A Flash Memory Cell Or An Array Of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：用于擦除闪存单元的方法或者具有改善的擦除耦合比的这样的单元阵列
公开(公告)号：US20090201744A1
公开(公告)日：2009-08-13
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

10. 发明授权

US07974136B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07974136B2
公开(公告)日：2011-07-05
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

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