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    • 1. 发明授权
      US06891220B2 Method of programming electrons onto a floating gate of a non-volatile memory cell 有权
    • Method of programming electrons onto a floating gate of a non-volatile memory cell
    • 将电子编程到非易失性存储单元的浮动栅极上的方法
    • US06891220B2
    • 2005-05-10
    • US10757830
    • 2004-01-13
    • Bing Yeh , Sohrab Kianian , Yaw Wen Hu
    • Bing Yeh , Sohrab Kianian , Yaw Wen Hu
    • H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
    • H01L27/105 , H01L27/11553
    • A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region. A method of programming the cell comprises the steps of creating an inversion layer in the second portion of the channel. A stream of electrons is generated at the drain region which is adjacent to the inversion layer, and the stream of electrons is passed through the inversion layer, reaching a pinch off point. The electrons are accelerated through the depletion region by the field lines from the floating gate, with little or no scattering, causing the electrons to be accelerated through the insulator, separating the floating gate from the substrate, and injected onto the floating gate.
    • 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。 编程单元的方法包括在通道的第二部分中创建反转层的步骤。 在与反转层相邻的漏极区域处产生电子流，并且电子流通过反转层，达到夹断点。 电子通过来自浮置栅极的场线通过耗尽区加速，几乎没有散射或不散射，导致电子通过绝缘体加速，将浮动栅极与衬底分离，并注入浮栅。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US07547603B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
    • Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
    • 具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
    • US07547603B2
    • 2009-06-16
    • US11520993
    • 2006-09-14
    • Bomy Chen , Sohrab Kianian , Yaw Wen Hu
    • Bomy Chen , Sohrab Kianian , Yaw Wen Hu
    • H01L21/336
    • H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
    • A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
    • 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07537996B2 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate 有权
    • Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate
    • 形成具有掩埋源极线和浮栅的浮栅存储器单元的半导体存储器阵列的自对准方法
    • US07537996B2
    • 2009-05-26
    • US11166882
    • 2005-06-24
    • Yaw Wen Hu , Sohrab Kianian
    • Yaw Wen Hu , Sohrab Kianian
    • H01L21/8247
    • H01L27/105 , H01L27/11553
    • A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
    • 一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US06952034B2 Semiconductor memory array of floating gate memory cells with buried source line and floating gate 有权
    • Semiconductor memory array of floating gate memory cells with buried source line and floating gate
    • 具有埋地源极线和浮栅的浮动存储单元的半导体存储器阵列
    • US06952034B2
    • 2005-10-04
    • US10358623
    • 2003-02-04
    • Yaw Wen Hu , Sohrab Kianian
    • Yaw Wen Hu , Sohrab Kianian
    • H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
    • H01L27/105 , H01L27/11553
    • A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
    • 一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07326614B2 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby 有权
    • Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
    • 形成具有掩埋位线和升高源极线的浮动栅极存储器单元的半导体存储器阵列的自对准方法以及由此制成的存储器阵列
    • US07326614B2
    • 2008-02-05
    • US10997382
    • 2004-11-23
    • Sohrab Kianian
    • Sohrab Kianian
    • H01L21/336
    • H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11556
    • A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped layer of conductive material having a first portion disposed over the channel region and a second portion extending vertically along the conductive block. The control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to the channel region. A portion of the control gate could extend into a trench formed into the substrate, wherein the drain region is formed underneath the trench, and the channel region has a first portion extending along the trench sidewall and a second portion extending along the substrate surface.
    • 形成浮置栅极存储单元阵列的方法，以及由其形成的阵列，其包括形成在衬底中的源极和漏极区域，以及设置在源极区域上的材料的导电块。 浮栅形成为薄的L形导电材料层，其具有设置在沟道区域上的第一部分和沿导电块垂直延伸的第二部分。 所述控制栅极包括与所述浮置栅极第一部分的远端相邻并绝缘的第一部分，以及邻近所述沟道区设置的第二部分。 控制栅极的一部分可以延伸到形成到衬底中的沟槽中，其中漏极区形成在沟槽下方，并且沟道区具有沿着沟槽侧壁延伸的第一部分和沿衬底表面延伸的第二部分。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      US20070007581A1 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
    • Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
    • 具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
    • US20070007581A1
    • 2007-01-11
    • US11520993
    • 2006-09-14
    • Bomy Chen , Sohrab Kianian , Yaw Hu
    • Bomy Chen , Sohrab Kianian , Yaw Hu
    • H01L29/788 , H01L21/336
    • H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
    • A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
    • 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US06917069B2 Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor 有权
    • Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
    • 具有埋置位线和垂直字线晶体管的浮动存储单元的半导体存储器阵列
    • US06917069B2
    • 2005-07-12
    • US09982413
    • 2001-10-17
    • Sohrab Kianian , Chih Hsin Wang
    • Sohrab Kianian , Chih Hsin Wang
    • H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
    • H01L27/11521 , H01L27/115 , H01L29/42332 , H01L29/7885
    • A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
    • 一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，以及由此形成的阵列，由此每个存储单元包括形成在半导体衬底的表面中的沟槽，间隔开的源极和漏极区域具有 沟道区域之间形成。 漏极区域形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁基本垂直地延伸的第一部分和沿着衬底的表面基本水平延伸的第二部分。 导电浮栅形成在沟道区的至少一部分和源极区的一部分之上并与之绝缘。 导电控制栅极形成为具有设置在沟槽中的第一部分和形成在浮动栅极上但与浮动栅极绝缘的第二部分。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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