专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07927994B1 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
标题翻译：具有浮置栅极，控制栅极，选择栅极和具有悬垂在浮动栅极上的擦除栅极的分流门非易失性闪存单元，阵列和制造方法
公开(公告)号：US07927994B1
公开(公告)日：2011-04-19
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

2. 发明申请

US20090039410A1 Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：分闸门非挥发性闪存单元，具有浮动栅极，控制栅极，选择栅极和具有悬垂在浮栅上的擦除栅极，阵列和制造方法
公开(公告)号：US20090039410A1
公开(公告)日：2009-02-12
申请号：US11834574
申请日：2007-08-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

3. 发明授权

US07868375B2 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing 有权
公开(公告)号：US07868375B2
公开(公告)日：2011-01-11
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

4. 发明申请

US20110076816A1 SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING 有权
标题翻译：分离闸门具有浮动门，控制门，选择门和在浮动门，阵列和制造方法上的过滤器的非挥发性闪存存储单元
公开(公告)号：US20110076816A1
公开(公告)日：2011-03-31
申请号：US12961193
申请日：2010-12-06
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

5. 发明申请

US20110127599A1 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing 审中-公开
标题翻译：具有浮动门的分闸门非易失性闪存单元，控制门，选择门和具有悬浮在浮动门上的擦除门，阵列和制造方法
公开(公告)号：US20110127599A1
公开(公告)日：2011-06-02
申请号：US13023443
申请日：2011-02-08
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： H01L29/788
CPC分类号： H01L29/42328 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

6. 发明申请

US20100054043A1 Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing 有权
标题翻译：具有浮动门的分流门非易失性闪存单元，控制栅极，选择栅极和擦除栅极，在浮动栅极上的突出，阵列和制造方法
公开(公告)号：US20100054043A1
公开(公告)日：2010-03-04
申请号：US12618632
申请日：2009-11-13
申请人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
发明人： Xian Liu , Amitay Levi , Alexander Kotov , Yuri Tkachev , Viktor Markov , James Yingbo Jia , Chien-Sheng Su , Yaw Wen Hu
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
摘要翻译：改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间和底物中的第二区域。单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

7. 发明申请

US20090201744A1 Method For Erasing A Flash Memory Cell Or An Array Of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：用于擦除闪存单元的方法或者具有改善的擦除耦合比的这样的单元阵列
公开(公告)号：US20090201744A1
公开(公告)日：2009-08-13
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

8. 发明授权

US07974136B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07974136B2
公开(公告)日：2011-07-05
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

9. 发明申请

US20110057247A1 FIN-FET Non-Volatile Memory Cell, And An Array And Method Of Manufacturing 有权
标题翻译： FIN-FET非易失性存储器单元，以及阵列和制造方法
公开(公告)号：US20110057247A1
公开(公告)日：2011-03-10
申请号：US12555756
申请日：2009-09-08
申请人： Yaw Wen Hu , Prateep Tuntasood
发明人： Yaw Wen Hu , Prateep Tuntasood
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate.
摘要翻译：非易失性存储单元具有在衬底层上具有第一导电类型的鳍状半导体构件的衬底层。翅片状构件具有第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，并且在第一区域和第二区域之间延伸的沟道区域。翅片状构件具有顶表面和在第一区域和第二区域之间的两个侧表面。字线与第一区域相邻并且电容耦合到沟道区域的第一部分的顶表面和两个侧表面。浮动栅极与字线相邻并且与顶表面绝缘并且电容耦合到沟道区的第二部分的两个侧表面。耦合栅极电容耦合到浮动栅极。擦除栅极与第二区域绝缘并且与浮栅和耦合栅极相邻。

10. 发明授权

US07547603B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
标题翻译：具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
公开(公告)号：US07547603B2
公开(公告)日：2009-06-16
申请号：US11520993
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式