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1. 发明授权

US06535424B2 Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage 有权
标题翻译：电压升压电路使用电源电压检测来补偿读取模式电压中的电源电压变化
公开(公告)号：US06535424B2
公开(公告)日：2003-03-18
申请号：US09915018
申请日：2001-07-25
申请人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
发明人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the VCC power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.
摘要翻译：闪存阵列系统和方法被公开用于产生电源调节升压电压，其中将电源电压施加到用于产生一个或多个电源的电源电压电平检测电路（例如，模数转换器，数字温度计）电压电平检测信号来自测量施加到升压电路的电源电压电平，其可以用作用于编程存储器单元的读取模式操作的升压字线电压，并且其中电源电压电平检测信号被施加到升压电压补偿电路以产生一个或多个升压电压补偿信号，所述升压电压补偿信号被施加到升压电路，所述升压电路可操作以产生用于编程核心单元的闪存阵列的调节升压电压。因此，公开了一种快速补偿装置，用于通常反映在提供给闪速存储器阵列的字线的升压电压电路的输出中的VCC电源变化，从而在读取模式期间产生字线电压，其基本上与电源电压。

2. 发明授权

US09021182B2 Flash memory for code and data storage 有权
标题翻译：用于代码和数据存储的闪存
公开(公告)号：US09021182B2
公开(公告)日：2015-04-28
申请号：US13250077
申请日：2011-09-30
申请人： Eungjoon Park , Robin John Jigour , Jooweon Park , Masaru Yano
发明人： Eungjoon Park , Robin John Jigour , Jooweon Park , Masaru Yano
IPC分类号： G06F12/02 , G11C11/00 , G11C16/04
CPC分类号： G06F3/061 , G06F3/0608 , G06F3/0658 , G06F3/0688 , G06F12/0246 , G06F2212/7208 , G11C11/005 , G11C16/0416 , G11C16/0483 , G11C2216/30
摘要： A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.
摘要翻译：用于代码和数据存储的快闪存储器包括具有快速读取访问和用于执行的适用性的代码存储器阵列，具有低位成本和高密度存储的特性的数据存储器阵列，以及提供对两者的访问的适当接口代码和数据。代码存储器阵列可以是NOR阵列或性能增强的NAND阵列。存储器可以在单个芯片封装或多芯片封装解决方案中实现。

3. 发明授权

US08018767B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08018767B2
公开(公告)日：2011-09-13
申请号：US12275121
申请日：2008-11-20
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

4. 发明授权

US07969787B2 Semiconductor device and control method of the same 有权
标题翻译：半导体器件及其控制方法相同
公开(公告)号：US07969787B2
公开(公告)日：2011-06-28
申请号：US12512638
申请日：2009-07-30
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/04
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

5. 发明申请

US20100299475A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF 有权
标题翻译：非挥发性半导体存储器件及其写入方法
公开(公告)号：US20100299475A1
公开(公告)日：2010-11-25
申请号：US12808265
申请日：2008-12-11
申请人： Masaru Yano
发明人： Masaru Yano
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C2216/14
摘要： A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.
摘要翻译：一种非易失性半导体存储器件，包括：非易失性存储器阵列，通过为每个存储单元设置多个不同的阈值电压来存储多个值;以及控制电路，控制对存储单元阵列的写入操作。当数据被写入存储单元时，控制电路选择一个相邻的字线，使用擦除电平进行比数据写入弱的写入，并验证一页的量的软编程，在相邻的存储单元中实现窄带擦除电平分布。

6. 发明授权

US07729169B2 Multiple programming of spare memory region for nonvolatile memory 有权
标题翻译：非易失性存储器的多余的备用存储区域编程
公开(公告)号：US07729169B2
公开(公告)日：2010-06-01
申请号：US12126686
申请日：2008-05-23
申请人： Masaru Yano , Akira Ogawa
发明人： Masaru Yano , Akira Ogawa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/28
摘要： Structures, methods, and systems for multiple programming of spare memory region for nonvolatile memory are disclosed. In one embodiment, a nonvolatile memory system comprises a main memory cell array, a spare memory cell array, and a memory controller that divides the spare memory cell array into at least a first region and a second region. The system further comprises a selection module for selecting the main memory cell array and the first region to write data and the first reference cell to write first reference data associated with the data during an initial data writing operation and for selecting the second region to write additional data and the second reference cell to write second reference data associated with the additional data during an additional data writing operation.
摘要翻译：公开了用于非易失性存储器的备用存储器区域的多次编程的结构，方法和系统。在一个实施例中，非易失性存储器系统包括主存储单元阵列，备用存储单元阵列和将备用存储单元阵列划分成至少第一区域和第二区域的存储器控制器。该系统还包括选择模块，用于选择主存储单元阵列和第一区域以写入数据，并且第一参考单元在初始数据写入操作期间写入与数据相关联的第一参考数据，并且用于选择第二区域以写入额外的数据数据和第二参考单元以在附加数据写入操作期间写入与附加数据相关联的第二参考数据。

7. 发明申请

US20060256617A1 Semiconductor device and method for controlling operation thereof 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20060256617A1
公开(公告)日：2006-11-16
申请号：US11316800
申请日：2005-12-22
申请人： Masaru Yano , Hideki Arakawa , Hidehiko Shiraiwa
发明人： Masaru Yano , Hideki Arakawa , Hidehiko Shiraiwa
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , G11C16/0491 , H01L27/115 , H01L29/792
摘要： A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate. The inversion layers are electrically connected to the global bit lines and a memory cell uses the inversion layers as a source and a drain.
摘要翻译：半导体器件包括在半导体衬底中形成用作局部位线的反型层的半导体衬底，字线，全局位线和反向栅极。反转层电连接到全局位线，并且存储单元使用反转层作为源极和漏极。

8. 发明申请

US20050286328A1 Semiconductor device and source voltage control method 有权
标题翻译：半导体器件和源极电压控制方法
公开(公告)号：US20050286328A1
公开(公告)日：2005-12-29
申请号：US11165008
申请日：2005-06-23
申请人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
发明人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
IPC分类号： G11C7/00 , G11C16/30
CPC分类号： G11C16/30
摘要： The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.
摘要翻译：在对数据进行编程之前，预充电电路用于预充电，该源电压线ARVSS的电压通常连接到同一扇区中提供的存储单元。在对数据进行编程之前，存储单元MC的源极线ARVSS的电压被预充电，并且即使数据编程期间是数据编程时，存储单元MC的源极线ARVSS的电压也不会降低缩短因此，可以在编程期间防止泄漏电流并且将数据最佳地编程到存储单元MC中。

9. 发明授权

US5995417A Scheme for page erase and erase verify in a non-volatile memory array 有权
标题翻译：在非易失性存储器阵列中进行页擦除和擦除验证的方案
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
IPC分类号： G11C16/02 , G11C16/16 , G11C16/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译：非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页被擦除和擦除验证。擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他连接到未选择用于页面擦除的字线的MOS晶体管。在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

10. 发明授权

US5926520A Shift register functioning in both latch mode and counter mode and flash memory employing same 失效
标题翻译：移位寄存器在锁存模式和计数器模式下工作，闪速存储器采用相同的方式
公开(公告)号：US5926520A
公开(公告)日：1999-07-20
申请号：US885174
申请日：1997-06-30
申请人： Masaru Yano
发明人： Masaru Yano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C19/00 , H03K21/00
CPC分类号： G11C16/06
摘要： The shift register includes a front stage latch portion for inputting input data when a clock signal is at a first level and latching the input data when the clock signal is at a second level, a rear stage latch portion for inputting data from the front stage latch portion when the clock signal is at the second level and latching the input data when the clock signal is at the first level, an input switch for connecting a data input terminal to the front stage latch portion when a mode switching signal is at a first level, and a feedback switch for connecting the rear stage latch portion to the front stage latch portion when the mode switching signal is at a second level. A latch mode clock signal is provided as the aforementioned clock signal when the mode switching signal is at the first level, and a counter mode clock signal or front stage shift register latch output signal is provided as the aforementioned clock signal when the mode switching signal is at the second level. The shift register functions in latch mode when the mode switching signal is at the first level, and functions with a plurality of stages thereof as a counter when at the second level. A flash memory equipped with the above shift registers which have a function whereby command flags of decoded external command signals are latched, and a counter function whereby counting is performed with the plural shift register stages.
摘要翻译：移位寄存器包括前级锁存部分，用于当时钟信号处于第一电平时输入输入数据，并且当时钟信号处于第二电平时锁存输入数据;后级锁存部分，用于从前级锁存器输入数据当时钟信号处于第二电平并且当时钟信号处于第一电平时锁存输入数据;当模式切换信号处于第一电平时用于将数据输入端连接到前级锁存器部分的输入开关以及反馈开关，用于当模式切换信号处于第二电平时将后级锁存部分连接到前级锁存器部分。当模式切换信号处于第一电平时，提供锁存模式时钟信号作为上述时钟信号，并且当模式切换信号为模式切换信号时，提供计数器模式时钟信号或前级移位寄存器锁存输出信号作为上述时钟信号在第二级。当模式切换信号处于第一电平时，移位寄存器在锁存模式下起作用，并且当处于第二电平时，以多个级作为计数器起作用。具有上述移位寄存器的闪速存储器具有锁定解码的外部命令信号的指令标志的功能，以及用多个移位寄存器级进行计数的计数器功能。

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