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1. 发明申请

US20090285019A1 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090285019A1
公开(公告)日：2009-11-19
申请号：US12512638
申请日：2009-07-30
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

2. 发明申请

US20070180184A1 Semiconductor device and control method therefor 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20070180184A1
公开(公告)日：2007-08-02
申请号：US11636111
申请日：2006-12-07
申请人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
发明人： Mototada Sakashita , Masaru Yano , Akira Ogawa , Tsutomu Nakai
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C2207/2263
摘要： The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.
摘要翻译：本发明提供一种用于控制具有多个非易失性存储单元的存储单元阵列的半导体器件的半导体器件和方法，该方法包括检测要写入的位数，作为从要编程的数据划分的划分数据进入存储单元阵列，将比特数与预定比特数进行比较，根据比特数与预定比特数比较的结果，反转或不反相除数数据以产生反转数据，并对反转数据进入存储单元阵列。该方法还包括检测要写入的比特数作为下一个分割数据，并将下一个分割数据的比特数与预定比特数进行比较，同时将反演数据编程到存储单元阵列中。

3. 发明申请

US20070002639A1 Semiconductor device and control method therefor 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20070002639A1
公开(公告)日：2007-01-04
申请号：US11478554
申请日：2006-06-28
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C5/14
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

4. 发明授权

US08705303B2 Semiconductor device and control method of the same 有权
标题翻译：半导体器件及其控制方法相同
公开(公告)号：US08705303B2
公开(公告)日：2014-04-22
申请号：US13413527
申请日：2012-03-06
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C7/00
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列中的核心单元的第一电流 - 电压转换电路，连接到参考单元的第二电流 - 电压转换电路参考单元数据线，感测来自第一电流 - 电压转换电路的输出和来自第二电流 - 电压转换电路的输出的读出放大器，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路以及如果在对所述参考单元数据线预充电期间所述参考单元数据线处的电压电平低于所述预定电压电平，则对所述参考单元数据线充电的充电电路。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

5. 发明授权

US08351268B2 Semiconductor device and control method of the same 有权
公开(公告)号：US08351268B2
公开(公告)日：2013-01-08
申请号：US13253634
申请日：2011-10-05
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C11/34
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

6. 发明申请

US20110032764A1 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20110032764A1
公开(公告)日：2011-02-10
申请号：US12905716
申请日：2010-10-15
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

7. 发明申请

US20070183193A1 Controlling a nonvolatile storage device 有权
标题翻译：控制非易失性存储设备
公开(公告)号：US20070183193A1
公开(公告)日：2007-08-09
申请号：US11639128
申请日：2006-12-13
申请人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
发明人： Masaru Yano , Hideki Arakawa , Mototada Sakashita , Akira Ogawa , Yoshiaki Shinmura , Hajime Aoki
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0475
摘要： A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.
摘要翻译：一种具有存储模式的非易失性存储装置的控制方法，其中根据在第一捕获区域中是否存在电荷而存储具有捕获电介质层1位数据的存储单元。在动态参考单元初始化操作中，作为初始化操作中的预设操作，在第一和第二动态参考单元的第二陷印区域上执行电荷累积操作，以对存储单元的第二陷印区域进行电荷累积操作。此外，在数据重写时，对第一捕获区域执行预编程验证和预编程。这使得可以缩短初始化和数据重写所花费的时间。

8. 发明授权

US07978523B2 Semiconductor device and control method of the same 有权
标题翻译：半导体器件及其控制方法相同
公开(公告)号：US07978523B2
公开(公告)日：2011-07-12
申请号：US12512741
申请日：2009-07-30
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/06
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：因此，本发明提供一种半导体存储器和控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

9. 发明申请

US20090290425A1 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090290425A1
公开(公告)日：2009-11-26
申请号：US12512741
申请日：2009-07-30
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/06 , G11C7/06
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefore, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：因此，本发明提供一种半导体存储器和控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

10. 发明授权

US07596032B2 Semiconductor device and control method therefor 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07596032B2
公开(公告)日：2009-09-29
申请号：US11478554
申请日：2006-06-28
申请人： Akira Ogawa , Masaru Yano
发明人： Akira Ogawa , Masaru Yano
IPC分类号： G11C16/06
CPC分类号： H01L27/1052 , G11C16/0466 , G11C16/28 , Y10T29/41
摘要： The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
摘要翻译：本发明提供一种半导体存储器及其控制方法，所述半导体器件包括连接到设置在非易失性存储单元阵列（10）中的核心单元（12）的第一电流 - 电压转换电路（16），第二电流 - 电压转换电路（26），通过参考单元数据线（24）连接到参考单元（22）;感测放大器（18），感测来自第一电流 - 电压转换电路的输出和来自第二电流电压转换电路，将参考单元数据线上的电压电平与预定电压电平进行比较的比较电路（28）以及对参考单元数据线充电的充电电路（30），如果参考单元数据线上的电压电平为在预充电参考单元数据线期间低于预定电压电平。根据本发明，可以缩短参考单元数据线的预充电周期，并且可以缩短数据读取时间。

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