专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050286328A1 Semiconductor device and source voltage control method 有权
标题翻译：半导体器件和源极电压控制方法
公开(公告)号：US20050286328A1
公开(公告)日：2005-12-29
申请号：US11165008
申请日：2005-06-23
申请人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
发明人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
IPC分类号： G11C7/00 , G11C16/30
CPC分类号： G11C16/30
摘要： The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.
摘要翻译：在对数据进行编程之前，预充电电路用于预充电，该源电压线ARVSS的电压通常连接到同一扇区中提供的存储单元。在对数据进行编程之前，存储单元MC的源极线ARVSS的电压被预充电，并且即使数据编程期间是数据编程时，存储单元MC的源极线ARVSS的电压也不会降低缩短因此，可以在编程期间防止泄漏电流并且将数据最佳地编程到存储单元MC中。

2. 发明授权

US07206232B2 Semiconductor device and source voltage control method 有权
标题翻译：半导体器件和源极电压控制方法
公开(公告)号：US07206232B2
公开(公告)日：2007-04-17
申请号：US11165008
申请日：2005-06-23
申请人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
发明人： Kazuhide Kurosaki , Shigekazu Yamada , Masaru Yano
IPC分类号： G11C11/34
CPC分类号： G11C16/30
摘要： The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.
摘要翻译：在对数据进行编程之前，预充电电路用于预充电，该源电压线ARVSS的电压通常连接到同一扇区中提供的存储单元。在对数据进行编程之前，存储单元MC的源极线ARVSS的电压被预充电，并且即使数据编程期间是数据编程时，存储单元MC的源极线ARVSS的电压也不会降低缩短因此，可以在编程期间防止泄漏电流并且将数据最佳地编程到存储单元MC中。

3. 发明授权

US08018767B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08018767B2
公开(公告)日：2011-09-13
申请号：US12275121
申请日：2008-11-20
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

4. 发明授权

US08325523B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08325523B2
公开(公告)日：2012-12-04
申请号：US13195722
申请日：2011-08-01
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明的实施例提供一种半导体器件，其包括：包括非易失性存储器单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明的一个实施例还提供了一种控制半导体器件的方法。

5. 发明授权

US07724071B2 Voltage boosting device and method for semiconductor device 有权
标题翻译：用于半导体器件的升压装置及方法
公开(公告)号：US07724071B2
公开(公告)日：2010-05-25
申请号：US11493467
申请日：2006-07-25
申请人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
发明人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
IPC分类号： G05F1/02
CPC分类号： G11C16/30 , G11C5/145
摘要： A semiconductor device includes: a pump circuit that boosts an output node connected to a memory cell array; an oscillator that outputs a clock to the pump circuit; and a detection circuit that outputs an actuating signal to the oscillator. In this semiconductor device, the actuating signal actuates the oscillator when the voltage of the output node of the pump circuit is lower than a first reference voltage, and the actuating signal stops the oscillator when the voltage of the output node is higher than a second reference voltage. In accordance with the present invention, when the voltage of the output node of the pump circuit is higher than the target voltage, the oscillator is stopped, and so is the pump circuit. Thus, unnecessary charge flow to the ground can be prevented, and the power consumption of the booster circuit can be reduced.
摘要翻译：一种半导体器件包括：泵电路，其对连接到存储单元阵列的输出节点进行升压; 一个向泵电路输出时钟的振荡器; 以及向振荡器输出启动信号的检测电路。在该半导体器件中，当泵电路的输出节点的电压低于第一参考电压时，致动信号致动振荡器，并且当输出节点的电压高于第二参考电压时，致动信号停止振荡器电压。根据本发明，当泵电路的输出节点的电压高于目标电压时，振荡器停止，泵电路停止。因此，可以防止不必要的电荷流向地面，并且可以降低升压电路的功耗。

6. 发明授权

US07468909B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07468909B2
公开(公告)日：2008-12-23
申请号：US11637260
申请日：2006-12-11
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C16/06 , G11C5/06
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

7. 发明申请

US20060077747A1 Semiconductor device and data reading method 审中-公开
标题翻译：半导体器件和数据读取方法
公开(公告)号：US20060077747A1
公开(公告)日：2006-04-13
申请号：US11228840
申请日：2005-09-16
申请人： Masaru Yano , Kazuhide Kurosaki , Kazuhiro Kitazaki
发明人： Masaru Yano , Kazuhide Kurosaki , Kazuhiro Kitazaki
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/02 , G11C7/18 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： The present invention has an arrangement that includes a Y decoder that selects a main bit line MBL to which sub bit lines SBL connected to memory cells MC are connected and selects main bit lines MBL adjacent to the selected main bit line MBL, and a YRST transistor that connects the adjacent main bit lines MBL to a given interconnection line and set these main bit lines to a given voltage. With this structure, it is possible to restrain noise from the adjacent main bit lines MBL to the minimum and prevent degradation of the voltage margin.
摘要翻译：本发明的结构包括：Y解码器，其选择与存储单元MC连接的子位线SBL连接的主位线MBL，并选择与所选择的主位线MBL相邻的主位线MBL;以及YRST晶体管其将相邻的主位线MBL连接到给定的互连线并将这些主位线设置为给定的电压。利用这种结构，可以将相邻主位线MBL的噪声抑制到最小，并且防止电压余量的劣化。

8. 发明申请

US20090109757A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20090109757A1
公开(公告)日：2009-04-30
申请号：US12275121
申请日：2008-11-20
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C16/04 , G11C5/14 , G11C7/00 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

9. 发明申请

US20070183211A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20070183211A1
公开(公告)日：2007-08-09
申请号：US11637260
申请日：2006-12-11
申请人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
发明人： Masaru Yano , Kazuhide Kurosaki , Mototada Sakashita
IPC分类号： G11C11/34 , G11C8/00 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/02 , G11C5/06 , G11C7/18 , G11C16/0408 , G11C16/0491 , G11C16/24 , G11C16/30
摘要： The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.
摘要翻译：本发明提供一种半导体器件，其包括：包括非易失性存储单元的存储单元阵列; 第一选择电路，连接或断开与形成其中一个存储单元的晶体管的源极和漏极连接到连接到第一电源的数据线DATAB; 以及第二选择电路，其将源极和漏极连接到或连接到连接到第二电源的地线ARVSS或从其断开。在该半导体装置中，第一选择电路和第二选择电路配置在存储单元阵列的相对侧。本发明还提供一种控制半导体器件的方法。

10. 发明申请

US20070085597A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20070085597A1
公开(公告)日：2007-04-19
申请号：US11493467
申请日：2006-07-25
申请人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
发明人： Akira Okada , Masaru Yano , Kazuhide Kurosaki
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C16/30 , G11C5/145
摘要： A semiconductor device includes: a pump circuit that boosts an output node connected to a memory cell array; an oscillator that outputs a clock to the pump circuit; and a detection circuit that outputs an actuating signal to the oscillator. In this semiconductor device, the actuating signal actuates the oscillator when the voltage of the output node of the pump circuit is lower than a first reference voltage, and the actuating signal stops the oscillator when the voltage of the output node is higher than a second reference voltage. In accordance with the present invention, when the voltage of the output node of the pump circuit is higher than the target voltage, the oscillator is stopped, and so is the pump circuit. Thus, unnecessary charge flow to the ground can be prevented, and the power consumption of the booster circuit can be reduced.
摘要翻译：一种半导体器件包括：泵电路，其对连接到存储单元阵列的输出节点进行升压; 一个向泵电路输出时钟的振荡器; 以及向振荡器输出启动信号的检测电路。在该半导体器件中，当泵电路的输出节点的电压低于第一参考电压时，致动信号致动振荡器，并且当输出节点的电压高于第二参考电压时，致动信号停止振荡器电压。根据本发明，当泵电路的输出节点的电压高于目标电压时，振荡器停止，泵电路停止。因此，可以防止不必要的电荷流向地面，并且可以降低升压电路的功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式