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1. 发明授权

US07153364B1 Re-circulation and reuse of dummy-dispensed resist 失效
标题翻译：虚拟分配抗蚀剂的再循环和再利用
公开(公告)号：US07153364B1
公开(公告)日：2006-12-26
申请号：US10000208
申请日：2001-10-23
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
IPC分类号： B05B1/28 , B05B15/04 , B05B3/00
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译：本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。虚拟分配的抗蚀剂返回到被采集的储存器。在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。来自分配头的抗蚀剂的流动在分配头保持抗干燥。通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

2. 发明授权

US06612319B1 Low defect EBR nozzle 有权
标题翻译：低缺陷EBR喷嘴
公开(公告)号：US06612319B1
公开(公告)日：2003-09-02
申请号：US09634670
申请日：2000-08-08
申请人： Bharath Rangarajan , Khoi A. Phan , Ursula Q. Quinto
发明人： Bharath Rangarajan , Khoi A. Phan , Ursula Q. Quinto
IPC分类号： B08B302
CPC分类号： H01L21/6708 , B05B15/52 , B05B15/531 , B05B15/55 , Y10S134/902
摘要： An edge bead removal system and method is provided that employs a nozzle for applying edge bead removal solvent to an edge bead of a photoresist material layer disposed on a wafer. The nozzle includes a liquid chamber that can be connected to a supply of edge bead removal and an air supply chamber that can be connected to a supply of air. The supply of air is isolated from the liquid supply chamber during application of the edge bead removal solvent and communicates via the air supply chamber to the liquid supply chamber after application of the edge bead removal solvent thus removing any droplets of edge bead removal solvent remaining in the nozzle tip. A system is also provided that includes an absorbent material that moves from a rest position, during application of the edge bead removal solvent, to an absorbing position that removes or catches any droplets of edge bead removal solvent remaining on the nozzle tip after application of the edge bead removal solvent is completed. A nozzle is also provided that includes a liquid supply chamber with an inner cylindrical surface that is made of or coated with either a hydrophobic material and/or a hydrophilic material.
摘要翻译：提供了一种边缘珠去除系统和方法，其采用用于将边缘珠去除溶剂施加到设置在晶片上的光致抗蚀剂材料层的边缘珠的喷嘴。喷嘴包括可以连接到边缘珠移除的供应的液体室和可以连接到空气供应的空气供应室。在施加边缘珠去除溶剂期间，空气的供应与液体供应室隔离，并且在施加边缘珠粒去除溶剂之后通过供气室与液体供应室连通，从而除去剩余的边缘珠去除溶剂中的任何液滴喷嘴尖端。还提供了一种系统，其包括吸收材料，其在施加边缘珠去除溶剂期间从静止位置移动到吸收位置，该吸收位置在施加之后移除或捕获留在喷嘴尖端上的边缘珠去除溶剂的任何液滴边缘珠去除溶剂完成。还提供了一种喷嘴，其包括具有由疏水材料和/或亲水材料制成或涂覆有内部圆柱形表面的液体供应室。

3. 发明授权

US07591902B2 Recirculation and reuse of dummy dispensed resist 有权
标题翻译：虚拟分配抗蚀剂的再循环和再利用
公开(公告)号：US07591902B2
公开(公告)日：2009-09-22
申请号：US11615080
申请日：2006-12-22
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
IPC分类号： B05B1/28 , B05B15/04 , B05B3/00 , B05C11/00
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译：本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。虚拟分配的抗蚀剂返回到被采集的储存器。在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。来自分配头的抗蚀剂的流动在分配头保持抗干燥。通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

4. 发明授权

US06593210B1 Self-aligned/maskless reverse etch process using an inorganic film 有权
标题翻译：使用无机膜的自对准/无掩模反向蚀刻工艺
公开(公告)号：US06593210B1
公开(公告)日：2003-07-15
申请号：US09707214
申请日：2000-11-06
申请人： Bharath Rangarajan , Bhanwar Singh , Ursula Q. Quinto
发明人： Bharath Rangarajan , Bhanwar Singh , Ursula Q. Quinto
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055 , H01L21/31058
摘要： One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.
摘要翻译：本发明的一个方面涉及一种在半导体衬底内形成沟槽隔离区域的方法，包括在半导体衬底中形成沟槽的步骤; 在所述衬底上沉积半保形介电材料，其中所述半保形介电材料具有位于所述沟槽上方的谷; 在半保形介电材料上形成无机保形膜; 抛光所述半导体衬底，由此去除所述无机保形膜的第一部分，从而暴露所述半共形绝缘材料的一部分，并且第二部分保留在所述半共形绝缘材料的所述谷的上方; 去除所述半共形介电材料的暴露部分; 并且平坦化衬底以提供其中具有介电材料的沟槽的半导体衬底。

5. 发明授权

US06439963B1 System and method for mitigating wafer surface disformation during chemical mechanical polishing (CMP) 失效
标题翻译：在化学机械抛光（CMP）期间减轻晶片表面变形的系统和方法
公开(公告)号：US06439963B1
公开(公告)日：2002-08-27
申请号：US09429428
申请日：1999-10-28
申请人： Bharath Rangarajan , Bhanwar Singh , Ursula Q. Quinto
发明人： Bharath Rangarajan , Bhanwar Singh , Ursula Q. Quinto
IPC分类号： B24B100
CPC分类号： B24B37/013 , B24B27/0076 , B24B37/04 , B24B49/12 , B24B49/16
摘要： The present invention relates to a system for mitigating wafer disformation. The system includes at least a first polishing pad and a second polishing pad for polishing a wafer surface. A CMP drive system selectively applys the first and second polishing pads against the wafer surface at first and second pressures, respectively. A measuring system measures a wafer surface thickness associated with a first circumferential region of the wafer polished by the first polishing pad and a wafer surface thickness associated with a second circumferential region of the wafer polished by the second polishing pad. A processor employs information from the measuring system to control the CMP drive system.
摘要翻译：本发明涉及一种减轻晶圆变形的系统。该系统至少包括用于抛光晶片表面的第一抛光垫和第二抛光垫。 CMP驱动系统分别在第一和第二压力下分别将第一和第二抛光垫施加在晶片表面上。测量系统测量与由第一抛光垫抛光的晶片的第一周向区域相关联的晶片表面厚度以及与由第二抛光垫抛光的晶片的第二周向区域相关联的晶片表面厚度。处理器采用来自测量系统的信息来控制CMP驱动系统。

6. 发明授权

US06210846B1 Exposure during rework for enhanced resist removal 有权
标题翻译：返修过程中的曝光增强抗蚀剂去除
公开(公告)号：US06210846B1
公开(公告)日：2001-04-03
申请号：US09373571
申请日：1999-08-13
申请人： Bharath Rangarajan , Ursula Q. Quinto , Bhanwar Singh
发明人： Bharath Rangarajan , Ursula Q. Quinto , Bhanwar Singh
IPC分类号： G03F900
CPC分类号： G03F7/425 , G03F7/40 , G03F7/42 , H01L21/0274 , H01L21/31133
摘要： A resist removal method provides for analyzing a patterned resist and determining if rework needs to be performed due to the pattern being incorrect. If the pattern is incorrect, the an entire upper surface of the patterned resist is exposed to mild UV light. The exposed patterned resist is then subjected to a developer, such as an alkaline bath, such that the exposed patterned resist is dissolved away from the substrate, and such that a new layer of resist can be applied and then patterned.
摘要翻译：抗蚀剂去除方法用于分析图案化的抗蚀剂并确定由于图案不正确而需要执行返工。如果图案不正确，则图案化的抗蚀剂的整个上表面暴露于温和的UV光。然后将曝光的图案化抗蚀剂经受诸如碱性浴的显影剂，使得暴露的图案化抗蚀剂溶解离开基底，并且使得可以施加新的抗蚀剂层然后被图案化。

7. 发明授权

US06221777B1 Reverse lithographic process for semiconductor vias 有权
标题翻译：半导体通孔反向光刻工艺
公开(公告)号：US06221777B1
公开(公告)日：2001-04-24
申请号：US09329154
申请日：1999-06-09
申请人： Bhanwar Singh , Bharath Rangarajan , Ursula Q. Quinto
发明人： Bhanwar Singh , Bharath Rangarajan , Ursula Q. Quinto
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L21/76802 , H01L21/76816
摘要： A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having a dielectric covered semiconductor device has a photoresist deposited which is patterned with vias in closely packed rows and columns. The resist is developed and trimmed to form via photoresist structures. A non-photosensitive polymer is deposited over the via photoresist structures and, when hardened, is subject to planarizing to expose the via photoresist structures. The via photoresist structures are removed and leave a reverse image patterned polymer. The photoresist is removed leaving the reverse image patterned polymer, which is then used to etch the dielectric to form vias to the semiconductor device.
摘要翻译：提供反向光刻工艺用于在半导体晶片上更密集地堆叠半导体。具有电介质覆盖的半导体器件的半导体晶片具有沉积的光致抗蚀剂，其以紧密堆积的行和列形成通孔。抗蚀剂被显影和修整以通过光致抗蚀剂结构形成。非光敏聚合物沉积在通孔光致抗蚀剂结构上，并且当硬化时，进行平面化以暴露通孔光致抗蚀剂结构。去除通孔光致抗蚀剂结构并留下反向图案图案化的聚合物。除去光致抗蚀剂留下反向图案图案化的聚合物，然后将其用于蚀刻电介质以形成到半导体器件的通孔。

8. 发明授权

US06562723B1 Hybrid stack method for patterning source/drain areas 失效
标题翻译：用于图案化源极/漏极区域的混合堆叠方法
公开(公告)号：US06562723B1
公开(公告)日：2003-05-13
申请号：US09430160
申请日：1999-10-29
申请人： Bharath Rangarajan , Jeffrey A. Shields , Ursula Q. Quinto
发明人： Bharath Rangarajan , Jeffrey A. Shields , Ursula Q. Quinto
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/32
摘要： A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack. An integrated circuit is also disclosed which is prepared by a process including: providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing a portion of the hybrid stack according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, building oxide structures on the underlying layer, and removing remaining portions of the hybrid stack.
摘要翻译：本文公开了一种制造集成电路的方法，该集成电路减少对下面的基层和所形成的氧化物结构的损害。该方法包括提供设置在下层上的混合堆叠，在混合堆叠上提供IC结构图案，根据IC结构图案选择性地去除顶层和底层的一部分，留下底层的保护部分根据IC结构图案，去除底层的保护部分，根据IC结构图案在下层中构建氧化物结构，并除去混合堆叠的剩余部分。还公开了一种集成电路，其通过以下处理制备，该方法包括：提供设置在下层上的混合堆叠，在混合堆叠上提供IC结构图案，根据IC结构图案选择性地去除混合堆叠的一部分，留下根据IC结构图案的底层的保护部分，在下层上构建氧化物结构，以及去除混合堆叠的剩余部分。

9. 发明授权

US06534243B1 Chemical feature doubling process 有权
标题翻译：化学特征加倍工艺
公开(公告)号：US06534243B1
公开(公告)日：2003-03-18
申请号：US10000493
申请日：2001-10-23
申请人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
发明人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
IPC分类号： G03F7039
CPC分类号： G03F7/405 , G03F7/0035 , G03F7/40
摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.
摘要翻译：在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括提供具有第一数目的结构特征的图案化抗蚀剂，所述图案化抗蚀剂包含酸催化聚合物; 使含有涂层材料的涂层，至少一种碱性化合物，光致酸发生剂和染料与图案化的抗蚀剂接触; 照射经涂覆的图案化抗蚀剂; 允许在图案化抗蚀剂的内部部分内形成去保护区; 并且去除涂层和去保护区域以提供第二数量的图案化抗蚀剂结构特征，其中第一数目小于第二数量。

10. 发明授权

US06362052B1 Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell 有权
标题翻译：在创建存储器单元期间使用蚀刻来减小抗蚀剂掩模的厚度和边缘周围
公开(公告)号：US06362052B1
公开(公告)日：2002-03-26
申请号：US09627567
申请日：2000-07-28
申请人： Bharath Rangarajan , Fei Wang , George Kluth , Ursula Q. Quinto
发明人： Bharath Rangarajan , Fei Wang , George Kluth , Ursula Q. Quinto
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.
摘要翻译：一种制造存储单元的方法，该方法包括形成覆盖半导体衬底的ONO层，沉积覆盖ONO层的抗蚀剂掩模，图案化抗蚀剂掩模，用n型掺杂剂注入半导体衬底，其中抗蚀剂掩模是用作离子注入掩模，并且在用n型掺杂剂注入半导体衬底时蚀刻抗蚀剂掩模。在一个优选实施例中，抗蚀剂掩模的蚀刻包括进行覆盖各向异性蚀刻以减小抗蚀剂掩模的厚度并且围绕抗蚀剂掩模的边缘。优选地，使用包括选自氮，氢，氯和氦的元素的蚀刻来进行覆盖层各向异性蚀刻。

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