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1. 发明授权

US06562723B1 Hybrid stack method for patterning source/drain areas 失效
标题翻译：用于图案化源极/漏极区域的混合堆叠方法
公开(公告)号：US06562723B1
公开(公告)日：2003-05-13
申请号：US09430160
申请日：1999-10-29
申请人： Bharath Rangarajan , Jeffrey A. Shields , Ursula Q. Quinto
发明人： Bharath Rangarajan , Jeffrey A. Shields , Ursula Q. Quinto
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/32
摘要： A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack. An integrated circuit is also disclosed which is prepared by a process including: providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing a portion of the hybrid stack according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, building oxide structures on the underlying layer, and removing remaining portions of the hybrid stack.
摘要翻译：本文公开了一种制造集成电路的方法，该集成电路减少对下面的基层和所形成的氧化物结构的损害。该方法包括提供设置在下层上的混合堆叠，在混合堆叠上提供IC结构图案，根据IC结构图案选择性地去除顶层和底层的一部分，留下底层的保护部分根据IC结构图案，去除底层的保护部分，根据IC结构图案在下层中构建氧化物结构，并除去混合堆叠的剩余部分。还公开了一种集成电路，其通过以下处理制备，该方法包括：提供设置在下层上的混合堆叠，在混合堆叠上提供IC结构图案，根据IC结构图案选择性地去除混合堆叠的一部分，留下根据IC结构图案的底层的保护部分，在下层上构建氧化物结构，以及去除混合堆叠的剩余部分。

2. 发明授权

US06426301B1 Reduction of via etch charging damage through the use of a conducting hard mask 有权
标题翻译：通过使用导电硬掩模减少通孔蚀刻充电损伤
公开(公告)号：US06426301B1
公开(公告)日：2002-07-30
申请号：US09628822
申请日：2000-07-31
申请人： Jeffrey A. Shields , Ramkumar Subramanian , Bharath Rangarajan , Allen S. Yu
发明人： Jeffrey A. Shields , Ramkumar Subramanian , Bharath Rangarajan , Allen S. Yu
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/743 , H01L21/76802
摘要： A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.
摘要翻译：一种晶片，具有衬底和绝缘层，该衬底包括在该绝缘层上的导电层。在蚀刻特征（例如通孔和沟槽）期间，导电层减轻在光致抗蚀剂层上形成的电荷。任何导电材料都可以用于此目的。例如，铝，氮化钽，钛和氮化钛。通常，等离子体蚀刻器用于在绝缘层中形成通路和沟槽以产生用于连接驻留在不同层内的器件的触点和导线。等离子体蚀刻器在蚀刻过程中利用的光致抗蚀剂层上引起电荷积聚。电荷积聚导致光致抗蚀剂层上的电位差，这可能导致器件的最终损坏。导电层消除了这种电位差，因为由于导电层的导电性而建立了电荷平衡。

3. 发明授权

US6127259A Phosphoric acid process for removal of contact BARC layer 有权
标题翻译：用于去除BARC层的磷酸工艺
公开(公告)号：US6127259A
公开(公告)日：2000-10-03
申请号：US372443
申请日：1999-08-11
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31111 , H01L21/76801
摘要： An anti-reflective coating layer which is used to provide better control over the photolithographic process during the contact masking step is removed using a boiling phosphoric acid bath to reduce the amount of thickness variations that remain after the metal contact is filled in the contact hole and planarized by polishing. As a result, post-polish defect inspections are facilitated.
摘要翻译：使用沸腾的磷酸浴除去用于在接触掩模步骤期间提供对光刻工艺的更好控制的抗反射涂层，以减少在接触孔中填充金属接触后留下的厚度变化量，通过研磨平坦化。结果，便利了后抛光缺陷检查。

4. 发明授权

US06551923B1 Dual width contact for charge gain reduction 失效
标题翻译：双宽度接点用于减少电荷增益
公开(公告)号：US06551923B1
公开(公告)日：2003-04-22
申请号：US09430845
申请日：1999-11-01
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829
摘要： A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, creating a second aperture in the first insulating layer below the first aperture, and filling the first and second apertures with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.
摘要翻译：本文公开了在集成电路中形成接触的方法。该方法包括在包括第一和第二栅极结构的半导体衬底之上提供第一绝缘层，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上方提供第二绝缘层，在第二绝缘层中形成第一孔在第一和第二栅极结构之间，在第一孔下面的第一绝缘层中形成第二孔，并用导电材料填充第一和第二孔以形成接触。第一孔具有第一孔径宽度并延伸到蚀刻停止层。第二孔径具有小于第一孔径宽度的第二孔径宽度。

5. 发明授权

US6153504A Method of using a silicon oxynitride ARC for final metal layer 有权
标题翻译：将氧氮化硅ARC用于最终金属层的方法
公开(公告)号：US6153504A
公开(公告)日：2000-11-28
申请号：US375004
申请日：1999-08-16
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L21/314 , H01L21/3213 , H01L21/60 , H01L21/28
CPC分类号： H01L24/11 , H01L21/32139 , H01L21/3143 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , Y10S438/952
摘要： A SiON ARC is formed on the uppermost metal or bonding pad layer, a topside protective layer, e.g., oxide, nitride or oxynitride, formed thereon and etching is conducted through the topside protective layer and SiON ARC to form a bonding pad opening. The use of SiON as an ARC reduces bonding pad etching time, enables a reduction in the height of the metal stack for reduced capacitance between metal lines and increased circuit speed, and improves etch marginality due to the reduced aspect ratio.
摘要翻译： SiON ARC形成在最上面的金属或焊盘层上，形成在其上的顶侧保护层，例如氧化物，氮化物或氧氮化物，并通过顶侧保护层和SiON ARC进行蚀刻以形成焊盘开口。 SiON作为ARC的使用减少了焊盘蚀刻时间，能够降低金属叠层的高度，以降低金属线之间的电容并提高电路速度，并且由于减小的纵横比而提高蚀刻边缘度。

6. 发明授权

US06441418B1 Spacer narrowed, dual width contact for charge gain reduction 有权
标题翻译：间距变窄，双宽度接触，减少电荷
公开(公告)号：US06441418B1
公开(公告)日：2002-08-27
申请号：US09430848
申请日：1999-11-01
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L31062
CPC分类号： H01L21/76829 , H01L21/76802 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.
摘要翻译：本文公开了在集成电路中形成接触的方法。该方法包括在包括第一和第二栅极结构的半导体衬底之上提供第一绝缘层，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上方提供第二绝缘层，在第二绝缘层中形成第一孔在第一和第二栅极结构之间，沿着第一孔的侧壁形成间隔物，在第一孔下方的第一绝缘层中形成第二孔，并用导电材料填充孔以形成接触。第一孔具有第一孔径宽度并延伸到蚀刻停止层。第二孔径具有小于第一孔径宽度的第二孔径宽度。

7. 发明授权

US06207582B1 Native oxide removal with fluorinated chemistry before cobalt silicide formation using nitride spacers 有权
标题翻译：在使用氮化物间隔物形成钴硅化物之前，使用氟化物进行原生氧化物去除
公开(公告)号：US06207582B1
公开(公告)日：2001-03-27
申请号：US09357767
申请日：1999-07-21
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L21301
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31116
摘要： A native oxide removal process utilizes a fluorinated plasma used in a sputter etch in order to remove the native oxide prior to a cobalt oxide formation process is initiated. The fluorinated plasma, such as CF4, is performed at between 50 to 100 volts bias on a substrate on which the native oxide is to be removed, and is performed in-situ. The fluorinated plasma provides both a chemical and a physical etching of the native oxide, without harming a gate oxide layer. The substrate is formed with nitride spacers and not oxide spacers, in order to lessen the possibility of any oxide being resputtered into the region in which the native oxide layer is being removed.
摘要翻译：自然氧化物去除方法利用溅射蚀刻中使用的氟化等离子体，以便在开始氧化钴形成过程之前除去天然氧化物。氟化等离子体，例如CF 4，在其上待除去天然氧化物的基底上的50至100伏偏压之间进行，并且原位进行。氟化等离子体对天然氧化物进行化学和物理蚀刻，而不会损害栅极氧化物层。衬底由氮化物间隔物而不是氧化物间隔物形成，以便减少任何氧化物被重新溅射到其中自然氧化物层被去除的区域中的可能性。

8. 发明授权

US06537866B1 Method of forming narrow insulating spacers for use in reducing minimum component size 有权
标题翻译：形成用于减小最小部件尺寸的窄绝缘间隔件的方法
公开(公告)号：US06537866B1
公开(公告)日：2003-03-25
申请号：US09691643
申请日：2000-10-18
申请人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
IPC分类号： H01L21338
CPC分类号： H01L29/66583 , H01L21/0331 , H01L21/0338 , H01L21/28123 , H01L21/31144 , H01L21/76802 , H01L21/76885
摘要： A method for forming insulating spacers for separating conducting layers in semiconductor wafer fabrication. The spacers are formed by removing portions of a protective photoresist layer through photolithography, and then through etching of exposed portions of the insulating layer. The spacers allow for fabrication of components that are smaller in size than are obtainable through conventional photolithography methods.
摘要翻译：一种在半导体晶片制造中形成用于分离导电层的绝缘间隔物的方法。通过光刻法去除保护光致抗蚀剂层的部分，然后通过蚀刻绝缘层的暴露部分来形成间隔物。间隔件允许制造尺寸小于通过常规光刻方法可获得的部件的部件。

9. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

10. 发明申请

US20090163018A1 Method to prevent alloy formation when forming layered metal oxides by metal oxidation 有权
标题翻译：通过金属氧化形成层状金属氧化物时防止合金形成的方法
公开(公告)号：US20090163018A1
公开(公告)日：2009-06-25
申请号：US12004124
申请日：2007-12-20
申请人： Steven Avanzino , Jeffrey A. Shields , Joffre Bernard , Suzette K. Pangrle
发明人： Steven Avanzino , Jeffrey A. Shields , Joffre Bernard , Suzette K. Pangrle
IPC分类号： H01L21/4763
CPC分类号： H01L21/31683 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and providing a second electrode on the oxidized metal body.
摘要翻译：制造电阻式存储器件的本方法包括以下步骤：提供第一电极，用氧化剂氧化第一电极的一部分，在第一电极的氧化部分上提供金属体，用金属体氧化整个金属体氧化剂，并在氧化的金属体上提供第二电极。

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