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1. 发明授权

US06309930B1 SRAM cell arrangement and method for manufacturing same 有权
标题翻译： SRAM单元布置及其制造方法
公开(公告)号：US06309930B1
公开(公告)日：2001-10-30
申请号：US09708636
申请日：2000-11-09
申请人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
发明人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
IPC分类号： H01L21336
CPC分类号： H01L27/11 , H01L27/1104
摘要： The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.
摘要翻译： SRAM单元布置包括每个存储单元的六个MOS晶体管，其被形成为垂直晶体管。 MOS晶体管布置在沟槽（G1，G2，G4）的侧壁处。诸如例如形成隔离物的栅极（Ga2，Ga4）或导电结构（L3）的存储单元的部分通过布置在衬底的表面（O）上方的相邻的水平导电结构（H5）接触 S）。存储器单元的部分之间的连接经由经由扩散区（D2）布置在凹陷和字线（W）的侧壁处的第三导电结构（L3），其经由衬底（S）内的凹陷的侧壁相邻的经由通过相对于垂直于表面（O）的轴线以不同高度部分布置的第二位线（B2）或/和经由导电结构（L1，L2，L6）的第一位线。触点（K5）同时接触MOS晶体管的多个部分。

2. 发明授权

US06222753B1 SRAM cell arrangement and method for manufacturing same 有权
标题翻译： SRAM单元布置及其制造方法
公开(公告)号：US06222753B1
公开(公告)日：2001-04-24
申请号：US09446419
申请日：1999-12-20
申请人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
发明人： Bernd Goebel , Emmerich Bertagnolli , Josef Willer , Barbara Hasler , Paul-Werner von Basse
IPC分类号： G11C700
CPC分类号： H01L27/11 , H01L27/1104
摘要： An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.
摘要翻译：每个存储单元包括六个MOS晶体管的SRAM单元布置，其中每个晶体管形成为垂直晶体管。 MOS晶体管布置在沟槽的侧壁。存储单元的部分，例如栅极电极或形成为间隔物的导电结构，经由布置在衬底表面上方的相邻的水平导电结构接触。存储器单元的部分之间的连接通过布置在凹陷和字线的侧壁处的第三导电结构经由第一位线经由第二位线和/或通孔的扩散区域经由衬底内的凹陷的侧壁相邻布置相对于垂直于表面的轴部分地布置在不同高度的导电结构。触头同时接触MOS晶体管的多个部分。

3. 发明授权

US6153475A Method for the manufacturing a memory cell configuration 失效
标题翻译：制造存储单元配置的方法
公开(公告)号：US6153475A
公开(公告)日：2000-11-28
申请号：US331495
申请日：1999-06-21
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/336
CPC分类号： H01L27/112
摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.
摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。第WO98 / 27586号公报日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置沿着沟槽（5）相邻的存储单元依次制造。特别是通过间隔物技术来确定相邻存储单元的间隔。通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。

4. 发明授权

US07239729B2 Circuit arrangement and method for operating a fingerprint sensor 有权
标题翻译：用于操作指纹传感器的电路布置和方法
公开(公告)号：US07239729B2
公开(公告)日：2007-07-03
申请号：US10203220
申请日：2001-02-07
申请人： Stephan Marksteiner , Paul-Werner von Basse
发明人： Stephan Marksteiner , Paul-Werner von Basse
IPC分类号： G06K9/00
CPC分类号： G06K9/0002
摘要： A circuit and method are provided for ensuring that a fingerprint sensor is started automatically when a finger is rested thereon such that a sufficiently contrasting image can be produced. A difference between a maximum and a minimum value of the sensor signals is generated wherein, if the difference is sufficiently large, indicating a sufficient contrast of an image to be produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint image is produced, a normal scanning operation of the fingerprint sensor is initiated, thus ensuring that the complete fingerprint images produced are of satisfactory quality.
摘要翻译：提供了一种电路和方法，用于确保当手指搁置在其上时自动启动指纹传感器，从而可以产生足够对比的图像。产生传感器信号的最大值和最小值之间的差异，其中如果该差值足够大，则指示要产生的图像的足够的对比度，则开始指纹传感器的正常扫描操作，从而确保产生完整的指纹图像，启动指纹传感器的正常扫描操作，从而确保生成的完整指纹图像质量令人满意。

5. 发明授权

US4126881A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4126881A
公开(公告)日：1978-11-21
申请号：US825225
申请日：1977-08-17
申请人： Paul-Werner von Basse , Rudiger Hofmann
发明人： Paul-Werner von Basse , Rudiger Hofmann
IPC分类号： G11C11/401 , G11C11/35 , G11C11/404 , H01L21/8242 , H01L27/07 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/06
CPC分类号： G11C11/404 , G11C11/35 , H01L27/0733 , H01L27/10823 , H01L29/7827 , Y10S257/911
摘要： A semiconductor memory has storage cells composed of MOS selector transistors operated by a drive line and storage capacitors connected to selector transistors. The selector transistors are constructed in accordance with the V-MOS technique. A semiconductor substrate is highly doped with atoms of one conductivity type and carries a buried layer highly doped with atoms of the opposite conductivity type. An epitaxial layer, weakly doped with atoms of the one conductivity type is carried over the buried layer and the semiconductor substrate. A second layer, highly doped with atoms of the opposite conductivity type, is carried over the epitaxial layer above the buried layer. A V-shaped groove divides the second layer into two sub-portions in the region of the storage cells and extends into the buried layer and a conductor path is disposed in the groove.
摘要翻译：半导体存储器具有由驱动线操作的MOS选择晶体管和连接到选择晶体管的存储电容器组成的存储单元。选择晶体管根据V-MOS技术构成。半导体衬底被高度掺杂有一种导电类型的原子，并且具有高度掺杂有相反导电类型的原子的掩埋层。在一个导电类型的原子上被弱掺杂的外延层承载在掩埋层和半导体衬底上。高掺杂有相反导电类型的原子的第二层被承载在掩埋层上方的外延层上。 V形槽将第二层在存储单元的区域中分成两个子部分并延伸到掩埋层中，并且导体路径设置在沟槽中。

6. 发明授权

US4136401A Storage module 失效
标题翻译：存储模块
公开(公告)号：US4136401A
公开(公告)日：1979-01-23
申请号：US745239
申请日：1976-11-26
申请人： Paul-Werner von Basse
发明人： Paul-Werner von Basse
IPC分类号： G11C11/401 , G11C11/404 , G11C11/40
CPC分类号： G11C11/404
摘要： A storage module includes single-transistor storage cells which are arranged between work lines and bit lines and form a cell field. The cell field is divided into two zones in that the bit lines are divided into two halves. A read out amplifier is arranged, in each case, between the two halves of each bit line, and at least one blank cell is arranged in each zone of the cell field in respect of each half of the bit line. The blank cells are designed to be identical to the storage cells and are selected during the operating interval of the storage cells of the cell field so that the storage capacitances of the blank cells are charged to the potential of the bit lines. At the time of selection of a word line of a zone of the cell field, the blank cells arranged in this zone are switched off.

7. 发明授权

US5831892A Matrix memory in virtual ground architecture 失效
标题翻译：虚拟地面架构中的矩阵存储器
公开(公告)号：US5831892A
公开(公告)日：1998-11-03
申请号：US904373
申请日：1997-08-01
申请人： Roland Thewes , Paul-Werner von Basse , Michael Bollu , Doris Schmitt-Landsiedel
发明人： Roland Thewes , Paul-Werner von Basse , Michael Bollu , Doris Schmitt-Landsiedel
IPC分类号： G11C11/56 , G11C17/12 , G11C17/00
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C2211/5631 , G11C2211/5634 , G11C7/1006
摘要： A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.
摘要翻译：具有改进的虚拟地面架构和评估电路的矩阵存储器，可以在读取事件期间在位线上同时读取两个相邻存储器单元的信息内容。具有信息“0”的存储单元例如由具有低阈值电压的各自的场效应晶体管实现。为读出提供的每个位线连接到同一行中的两个相邻场效应晶体管的漏极端子。源端子被施加到彼此不同的两个电位之一。取决于在选择相关字线时场效应晶体管是导通的，在位线上获得不同的合成电位。然后将这些电位在评估电路中转换为表示读取信息的二进制信号。

8. 发明授权

US4958319A Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs 失效
标题翻译：地址放大器电路具有自动互锁和防止多次寻址，用于静态GaAs RAM
公开(公告)号：US4958319A
公开(公告)日：1990-09-18
申请号：US409578
申请日：1989-09-19
申请人： Paul-Werner von Basse , Jean-Marc Dortu , Andrea Herlitzek , Dieter Kohlert , Ulrich Schaper
发明人： Paul-Werner von Basse , Jean-Marc Dortu , Andrea Herlitzek , Dieter Kohlert , Ulrich Schaper
IPC分类号： G11C11/413 , G11C11/418
CPC分类号： G11C11/418
摘要： Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs. In the address amplifier circuit the address is doubly stored and only those signals that cannot trigger a misdecoding are forwarded from the address amplifier to a decoder circuit.
摘要翻译：地址放大器电路具有自动互锁和防止多次寻址，用于静态GaAs RAM。在地址放大器电路中，地址被双重存储，只有那些不能触发错误解码的信号从地址放大器转发到解码器电路。

9. 发明授权

US6138227A Device for the jump-like addressing of specific lines of a serially operating digital memory 失效
标题翻译：用于串行操作数字存储器的特定线路的跳转寻址的设备
公开(公告)号：US6138227A
公开(公告)日：2000-10-24
申请号：US43046
申请日：1998-03-13
申请人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu
发明人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu
IPC分类号： G11C8/04 , G06F12/02
CPC分类号： G11C8/04
摘要： A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.
摘要翻译： PCT No.PCT / DE96 / 01511 Sec。 371日期1998年3月13日 102（e）1998年3月13日PCT PCT 1996年8月13日PCT公布。公开号WO97 / 10600 日期1997年3月20日具有行和列的存储单元的数字存储器矩阵，存储器单元的寻址由执行地址的任意跳跃的控制设备实现，从而避免在相邻行上寻址。跳跃增量可选。控制装置是控制链，其中两个被提供，并且控制链的输出连接到链接元件，连接元件又连接到存储器线。连接元件分组提供。

10. 发明授权

US6097661A Pointer circuit with low surface requirement high speed and low power loss 失效
标题翻译：指针电路具有低表面要求高速和低功耗
公开(公告)号：US6097661A
公开(公告)日：2000-08-01
申请号：US161004
申请日：1998-09-25
申请人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
发明人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
IPC分类号： G11C19/28 , G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.
摘要翻译：在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器端子（Q，+ E，ovs Q + EE）。两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。存储器由时钟信号控制。这导致有利的表面要求和功率损耗低以及高速度。

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