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    • 1. 发明授权
    • Semiconductor memory
    • 半导体存储器
    • US4126881A
    • 1978-11-21
    • US825225
    • 1977-08-17
    • Paul-Werner von BasseRudiger Hofmann
    • Paul-Werner von BasseRudiger Hofmann
    • G11C11/401G11C11/35G11C11/404H01L21/8242H01L27/07H01L27/10H01L27/108H01L29/78H01L29/06
    • G11C11/404G11C11/35H01L27/0733H01L27/10823H01L29/7827Y10S257/911
    • A semiconductor memory has storage cells composed of MOS selector transistors operated by a drive line and storage capacitors connected to selector transistors. The selector transistors are constructed in accordance with the V-MOS technique. A semiconductor substrate is highly doped with atoms of one conductivity type and carries a buried layer highly doped with atoms of the opposite conductivity type. An epitaxial layer, weakly doped with atoms of the one conductivity type is carried over the buried layer and the semiconductor substrate. A second layer, highly doped with atoms of the opposite conductivity type, is carried over the epitaxial layer above the buried layer. A V-shaped groove divides the second layer into two sub-portions in the region of the storage cells and extends into the buried layer and a conductor path is disposed in the groove.
    • 半导体存储器具有由驱动线操作的MOS选择晶体管和连接到选择晶体管的存储电容器组成的存储单元。 选择晶体管根据V-MOS技术构成。 半导体衬底被高度掺杂有一种导电类型的原子,并且具有高度掺杂有相反导电类型的原子的掩埋层。 在一个导电类型的原子上被弱掺杂的外延层承载在掩埋层和半导体衬底上。 高掺杂有相反导电类型的原子的第二层被承载在掩埋层上方的外延层上。 V形槽将第二层在存储单元的区域中分成两个子部分并延伸到掩埋层中,并且导体路径设置在沟槽中。
    • 3. 发明授权
    • Broadband signal space switching device
    • 宽带信号空间切换装置
    • US4745409A
    • 1988-05-17
    • US919700
    • 1986-10-16
    • Rudiger Hofmann
    • Rudiger Hofmann
    • H03K19/094H04N7/14H04Q3/52H04Q9/00
    • H03K19/09429H04Q3/521
    • In a broadband signal space switching device, the respective switching elements are controllable by a decoder-controlled, crosspoint-associated memory cell and are respectively formed with a CMOS inverter circuit having MOS transistors of the enhancement type which lie between a switching element input and a switching element output. A further p-channel transistor, likewise of the enhancement type, is inserted between the p-channel enhancement transistor and the appertaining feed voltage source and a further n-channel transistor, likewise of the enhancement type, is inserted between the n-channel enhancement transistor and the appertaining feed voltage source. The control electrodes of the further enhancement transistors are connected to the outputs of the memory cell.
    • 在宽带信号空间切换装置中,相应的开关元件由解码器控制的交叉点相关联的存储器单元控制,并且分别形成有具有增强型MOS晶体管的CMOS反相器电路,该MOS晶体管位于开关元件输入和 开关元件输出。 类似于增强型的另一个p沟道晶体管被插入在p沟道增强晶体管和相应的馈电电压源之间,并且类似于增强型的另外的n沟道晶体管被插入在n沟道增强 晶体管和馈源电压源。 另外的增强晶体管的控制电极连接到存储单元的输出端。