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    • 5. 发明授权
    • DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties
    • 其存储单元可以具有晶体管和具有改善的电性能的电容器的DRAM单元配置
    • US06586795B2
    • 2003-07-01
    • US09873659
    • 2001-06-04
    • Bernd GoebelEmmerich Bertagnolli
    • Bernd GoebelEmmerich Bertagnolli
    • H01L218242
    • H01L27/10864H01L27/10841
    • Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches. Above the recess, an insulating structure is preferably disposed in the first indentation and adjoins two adjacent ones of the insulation trenches.
    • 每个存储单元包括一个晶体管和一个电容器。 电容器的存储节点设置在第一压痕中,而晶体管的栅电极设置在第二压痕中。 晶体管的上源极/漏极区域,沟道区域和下部源极/漏极区域彼此并排设置,并且每个与第一压痕的第一侧面和第二压痕相邻。 第一侧面的至少一部分设置有电容器电介质,其在下源极/漏极区域的区域中具有凹槽,其中存储器节点邻接下部源极/漏极区域。 存储器单元中的第一个存储单元的第二缩进可以与布置在第二个存储单元的第一个凹槽中的存储器节点相邻。 第二个凹痕可以是横向延伸到绝缘沟槽的字线沟槽的部分。 在凹部上方,绝缘结构优选设置在第一压痕中,并与两个绝缘沟槽相邻。
    • 6. 发明授权
    • Process for producing semiconductor components between which contact is
made vertically
    • 用于制造在其之间进行触点的半导体部件的制造方法
    • US5767001A
    • 1998-06-16
    • US545650
    • 1995-11-03
    • Emmerich BertagnolliHelmut Klose
    • Emmerich BertagnolliHelmut Klose
    • H01L21/768H01L23/48H01L25/065H01L27/00H01L27/06H01L21/283H01L21/302
    • H01L25/0657H01L21/76898H01L23/481H01L25/50H01L27/0688H01L2225/06513H01L2225/06524H01L2225/06541H01L2924/0002
    • A process for producing components having a contact structure provides for vertical contact-making, in which, for the connection of a metal contact of a first component to a metal contact of a second component, the substrate is etched out, starting from the top, in a region provided for a vertical, conductive connection, this recess is filled with a metal so that said metal is connected to the surface of the metal contact, the rear side of the substrate is removed until the metal projects beyond the rear side, a metallization layer made of a metal having a low melting point, for example AuIn, is applied to the metal contact of the second component, the surface of the second component is provided with a planar layer, the two components are arranged vertically with respect to one another and a permanent contact is produced between the metal of the first component and the metallization layer of the second component by pressing one onto the other and heating.
    • PCT No.PCT / DE94 / 00486 Sec。 371日期:1995年11月3日 102(e)1995年11月3日日期PCT 1994年5月2日PCT PCT。 WO94 / 25981 PCT公开 日期1994年11月10日具有接触结构的部件的制造方法提供垂直接触,其中为了将第一部件的金属接触件与第二部件的金属接触件连接,蚀刻出基板, 从顶部开始,在设置用于垂直导电连接的区域中,该凹部填充有金属,使得所述金属连接到金属接触件的表面,基板的后侧被移除,直到金属突出超出 背面,由具有低熔点的金属(例如AuIn)制成的金属化层被施加到第二部件的金属接触件,第二部件的表面设置有平面层,两个部件被布置 在第一部件的金属和第二部件的金属化层之间通过将其彼此挤压并加热而产生永久接触。
    • 7. 发明授权
    • Method for manufacturing a bipolar transistor
    • 制造双极晶体管的方法
    • US5217909A
    • 1993-06-08
    • US712563
    • 1991-06-10
    • Emmerich Bertagnolli
    • Emmerich Bertagnolli
    • H01L29/73H01L21/285H01L21/331H01L21/60H01L29/732H01L29/737
    • H01L21/76897H01L21/28525H01L29/66272Y10S148/01Y10S148/011
    • A method for manufacturing a bipolar transistor in which the base, emitter and collector terminals are produced from a single, planar layer of, for example, polysilicon, directly deposited onto a substrate. The planar layer is doped by a first conductivity type for the base terminal. After masking with an implantation mask, covering a region of the planar layer for the base terminal and defining regions of the planar layer for the emitter and collector terminals, the regions for the emitter and collector terminals are doped by an implantation of a second conductivity type, the second conductivity type being opposite the first conductivity type. After a self-aligned supplementation of the implantation mask, for example, with the assistance of a spacer technique, with which the regions of the planar layer for the emitter and collector terminals are also covered, the planar layer is structured by anisotropic etching by using the supplemented implantation mask as an etching mask.
    • 一种用于制造双极晶体管的方法,其中基极,发射极和集电极端子由直接沉积到衬底上的例如多晶硅的单个平面层产生。 平面层由基极端子的第一导电类型掺杂。 在用注入掩模掩蔽之后,覆盖用于基极端子的平面层的区域并限定用于发射极和集电极端子的平面层的区域,通过第二导电类型的注入来掺杂发射极和集电极端子的区域 第二导电类型与第一导电类型相反。 在注入掩模的自对准补充之后,例如,借助间隔技术,用于发射极和集电极端子的平面层的区域也被覆盖,平面层通过使用 补充的植入掩模作为蚀刻掩模。