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1. 发明授权

US06510534B1 Method and apparatus for testing high performance circuits 有权
标题翻译：用于测试高性能电路的方法和装置
公开(公告)号：US06510534B1
公开(公告)日：2003-01-21
申请号：US09607128
申请日：2000-06-29
申请人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek , Jean-Francois Cote
IPC分类号： G01R3128
CPC分类号： G11C29/56012 , G01R31/318552 , G01R31/318563 , G11C29/56 , G11C2029/3202
摘要： A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks. The test clock can be an independent and asynchronous clock or derived from the system clock. The test can also be performed by using only the test clock in the case only the test clock is available or for diagnostic and debug purposes.
摘要翻译：通过在移位序列之后的捕获序列期间能够进行至少两个时钟脉冲来执行用于速度测试高性能数字系统和具有组合逻辑和存储元件可能是可扫描和不可扫描的电路的方法。该方法提供了在执行速度测试之前在测试开始时经由可扫描存储器元件的任何非可扫描存储器元件的初始化。在初始化期间，控制逻辑产生一个信号，以禁止生成用于捕获的系统时钟脉冲。相反，仅产生从测试时钟或系统时钟得到的一个时钟周期来初始化不可扫描元件。所需的移位序列的数量取决于两个可扫描存储器元件之间必须经过的不可扫描元件的最大数量。在相同的初始化期间，输出响应分析器被禁用，因为未知数据值将出现在数据流中。一个测试控制器是一个测试时钟，它包括一个产生移位和捕捉时钟的时钟生成模块。测试时钟可以是独立的和异步的时钟，也可以从系统时钟导出。只有在测试时钟可用或用于诊断和调试目的的情况下，也可以仅使用测试时钟进行测试。

2. 发明申请

US20050240790A1 Clocking methodology for at-speed testing of scan circuits with synchronous clocks 有权
标题翻译：具有同步时钟的扫描电路的高速测试时钟方法
公开(公告)号：US20050240790A1
公开(公告)日：2005-10-27
申请号：US11060407
申请日：2005-02-18
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote , Fadi Maamari
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote , Fadi Maamari
IPC分类号： G01R31/3185 , G06F13/42
CPC分类号： G01R31/31858
摘要： A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
摘要翻译：一种用于对扫描电路中相互作用的同步时钟域的跨域路径中的延迟缺陷进行高速扫描测试的时钟方法，每个路径源自一个域中的源存储器元件，并终止于另一个的另一个中的目的地存储器元件所述域并且包括选择性地将每个域的时钟的捕获边缘或启动边缘与交互的同步时钟域的至少一个其他域的相应边缘对准，以确定要在源域之间测试的跨域路径和目的域; 以各个域时钟速率在每个域中计时存储器元件以从源域中的源存储器元件启动信号转换; 并且对于正在测试的每对相互作用的时钟域，在目的地域中捕获对源自源域的路径发射的信号转换的电路响应，并且选择性地禁止在源域中捕获沿着路径发射的信号转换的电路响应源自目的地域。

3. 发明授权

US06457161B1 Method and program product for modeling circuits with latch based design 有权
标题翻译：用于基于闩锁设计的电路建模方法和程序产品
公开(公告)号：US06457161B1
公开(公告)日：2002-09-24
申请号：US09817298
申请日：2001-03-27
申请人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
发明人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.
摘要翻译：一种用于对具有组合逻辑和锁存器的逻辑电路进行建模的方法和计算机程序产品，其中锁存器由第一时钟相位，第二时钟相位或从第二时钟相位导出的脉冲之一计时，锁存器的子集可扫描的，包括对于逻辑电路中的每个锁存器，将锁存器与第一和第二时钟相位之一相关联; 并且当锁存器与第一时钟相关联时，将锁存器建模为连接在锁存器的数据输入和输出之间的缓冲器; 并且当锁存器与第二时钟相关联时，将锁存器建模为具有与锁存器相同的数据输入，数据输出和时钟输入的边沿触发触发器。

4. 发明申请

US20050273683A1 Insertion of embedded test in RTL to GDSII flow 审中-公开
标题翻译：嵌入式测试在RTL中插入GDSII流程
公开(公告)号：US20050273683A1
公开(公告)日：2005-12-08
申请号：US11144764
申请日：2005-06-06
申请人： Jean-Francois Cote , Benoit Nadeau-Dostie , Fadi Maamari
发明人： Jean-Francois Cote , Benoit Nadeau-Dostie , Fadi Maamari
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50
CPC分类号： G01R31/318583
摘要： A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of the circuit into an unmapped circuit description; extracting information from the unmapped circuit description for use in generating and inserting RTL descriptions of test objects into the RTL circuit description and for use in generating and inserting scan chains into the circuit; generating and inserting the RTL descriptions of the test objects into the RTL circuit description to produce a modified RTL circuit description; storing the modified RTL circuit description; synthesizing the modified RTL description into a gate level circuit description of the circuit; and constructing and inserting scan chains into the gate level circuit description according to information extracted from the unmapped circuit description.
摘要翻译：一种设计具有用于扫描测试电路的嵌入式测试对象的可扫描可测集成电路的方法，包括将电路的寄存器传输电平（RTL）电路描述编译成未映射电路描述; 从未映射电路描述中提取信息，用于生成和插入测试对象的RTL描述到RTL电路描述中，并用于生成和插入扫描链到电路中; 生成并将测试对象的RTL描述插入到RTL电路描述中，以产生修改的RTL电路描述; 存储修改的RTL电路描述; 将修改的RTL描述合成到电路的门级电路描述中; 以及根据从未映射电路描述提取的信息构建并将扫描链插入到门级电路描述中。

5. 发明授权

US06615392B1 Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby 有权
标题翻译：分层设计和测试方法和系统，程序产品体现了由此产生的方法和集成电路
公开(公告)号：US06615392B1
公开(公告)日：2003-09-02
申请号：US09626877
申请日：2000-07-27
申请人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
发明人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
IPC分类号： G06F945
CPC分类号： G01R31/318591 , G01R31/318586
摘要： A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
摘要翻译：一种在具有至少一个模块的集成电路的分级设计中使用的方法，每个模块具有功能存储元件和组合逻辑，该方法包括读取电路的描述; 用扫描模式和捕获模式可配置的可扫描存储器元件的描述代替模块的每个功能存储元件的描述; 通过将所选择的可扫描存储器元件的描述转换为在内部测试模式，外部测试模式和正常操作模式中可配置的外围可扫描存储器元件的描述，将每个模块分成内部分区和外围分区; 修改电路描述中的模块的描述，以便将存储器元件布置成扫描链，其中当配置在内部测试模式中时，由模块测试控制器控制每个模块的外围和内部可扫描存储元件; 并且当在外部测试模式下配置时，每个模块的外围可扫描存储器元件由顶级测试控制器控制; 并验证电路的内部测试模式和外部测试模式的正确操作。

6. 发明授权

US07424656B2 Clocking methodology for at-speed testing of scan circuits with synchronous clocks 有权
标题翻译：具有同步时钟的扫描电路的高速测试时钟方法
公开(公告)号：US07424656B2
公开(公告)日：2008-09-09
申请号：US11060407
申请日：2005-02-18
申请人： Benoit Nadeau-Dostie , Jean-François Côté , Fadi Maamari
发明人： Benoit Nadeau-Dostie , Jean-François Côté , Fadi Maamari
IPC分类号： G01R31/28
CPC分类号： G01R31/31858
摘要： A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal transitions launched along paths originating from the destination domain.
摘要翻译：一种用于对扫描电路中相互作用的同步时钟域的跨域路径中的延迟缺陷进行高速扫描测试的时钟方法，每个路径源自一个域中的源存储器元件，并终止于另一个的另一个中的目的地存储器元件所述域并且包括选择性地将每个域的时钟的捕获边缘或启动边缘与交互的同步时钟域的至少一个其他域的相应边缘对准，以确定要在源域之间测试的跨域路径和目的域; 以各个域时钟速率在每个域中计时存储器元件以从源域中的源存储器元件启动信号转换; 并且对于正在测试的每对相互作用的时钟域，在目的地域中捕获对源自源域的路径发射的信号转换的电路响应，并且选择性地禁止在源域中捕获沿着路径发射的信号转换的电路响应源自目的地域。

7. 发明授权

US07191374B2 Method of and program product for performing gate-level diagnosis of failing vectors 有权
标题翻译：用于执行故障向量的门级诊断的方法和程序产品
公开(公告)号：US07191374B2
公开(公告)日：2007-03-13
申请号：US10435094
申请日：2003-05-12
申请人： Fadi Maamari , Sonny Ngai San Shum , Benoit Nadeau-Dostie
发明人： Fadi Maamari , Sonny Ngai San Shum , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/2891 , G01R31/3177
摘要： A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.
摘要翻译：一种具有故障测试向量的集成电路的故障诊断方法，具有使用通过仿真一组测试向量获得的故障候选故障效应的具有观察到的故障效应的故障诊断方法，包括确定每个故障候选的故障候选诊断测量，所述故障候选诊断测量具有故障候选匹配度量，观察到的故障效应不匹配度量和故障候选激励度量，降低诊断测量顺序对故障候选进行排序; 并且将具有最高诊断度量的故障候选者识别为观察到的故障效应的最可能的原因。

8. 发明申请

US20050240848A1 Masking circuit and method of masking corrupted bits 审中-公开
标题翻译：掩蔽电路和掩蔽损坏位的方法
公开(公告)号：US20050240848A1
公开(公告)日：2005-10-27
申请号：US11109844
申请日：2005-04-20
申请人： Jean-Francois Cote , Paul Price , Benoit Nadeau-Dostie
发明人： Jean-Francois Cote , Paul Price , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318572
摘要： A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.
摘要翻译：一种屏蔽电路，用于在集成电路的扫描测试期间有选择地屏蔽扫描链输入和/或输出，包括屏蔽寄存器，其具有用于每个扫描链的至少两个屏蔽寄存器元件，以提供多个屏蔽模式; 以及用于每个扫描链的输入和输出掩模控制电路，每个掩模控制电路连接在测试图案源和签名寄存器之间，并且连接在相关联的扫描链的串行输入和串行输出之间，并响应于存储的掩码控制数据在用于在电路的扫描测试期间用于将多个掩模模式中的一个掩模模式中的一个配置为关联的扫描链的寄存器元件中。

9. 发明申请

US20050240847A1 Clock controller for at-speed testing of scan circuits 有权
标题翻译：时钟控制器，用于扫描电路的高速测试
公开(公告)号：US20050240847A1
公开(公告)日：2005-10-27
申请号：US11013319
申请日：2004-12-17
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31858 , G01R31/318552 , G01R31/31922
摘要： A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a test response patterns from the scan chains and for generating a burst phase signal after loading a test pattern; and a burst clock controller associated with each of one or more clock domains and responsive to a burst phase signal for generating a burst of clock pulses derived from a respective reference clocks and including a first group of burst clock pulses having a selected reduced frequency relative to the reference clock and a second group of burst clock pulses having a frequency corresponding to that of the reference clock.
摘要翻译：一种测试时钟控制器，用于在具有一个或多个时钟域的集成电路中产生用于扫描链的测试时钟信号，包括移位时钟控制器，用于产生用于将测试模式加载到时钟域中的扫描链中并用于卸载的移位时钟信号来自扫描链的测试响应模式并且用于在加载测试模式之后产生突发相位信号; 以及突发时钟控制器，其与一个或多个时钟域中的每一个相关联，并且响应于脉冲串相位信号，用于产生从各个参考时钟导出的时钟脉冲串，并且包括相对于相对参考时钟具有选定的降低的频率的第一组脉冲串时钟脉冲参考时钟和具有与参考时钟的频率对应的频率的第二组突发时钟脉冲。

10. 发明授权

US6000051A Method and apparatus for high-speed interconnect testing 失效
标题翻译：高速互连测试的方法和装置
公开(公告)号：US6000051A
公开(公告)日：1999-12-07
申请号：US948842
申请日：1997-10-10
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31855
摘要： A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.-- In operation in all of the components concurrently at the rate of the Test Clock; performing the Update and Capture Operations in the first group of components at the rate of the Test Clock; and performing the Update and Capture Operations in the second group of components at the rate of the system Clock. The method employs a novel integrated circuit, test controller and boundary scan cells.
摘要翻译：一种测试具有可在高速系统时钟操作的部件的电路板的高速互连性的方法，采用IEEE 1149.1标准测试方法，其中测试数据在Shift-In期间以测试时钟的速率被移入和移出部件， Shift-Out操作，并且在Shift-In和Shift-Out操作之间具有Update操作和Capture操作，这些组件包括能够以仅测试时钟的速率执行Update和Capture操作的第一组组件，以及能够以系统时钟的速率执行更新和捕获操作的第二组组件，所述方法包括以所述测试时钟的速率同时在所有组件中执行所述移位操作的步骤; 以测试时钟的速率在第一组组件中执行更新和捕获操作; 并以系统时钟的速率在第二组组件中执行更新和捕获操作。该方法采用新颖的集成电路，测试控制器和边界扫描单元。

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