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1. 发明授权

US6000051A Method and apparatus for high-speed interconnect testing 失效
标题翻译：高速互连测试的方法和装置
公开(公告)号：US6000051A
公开(公告)日：1999-12-07
申请号：US948842
申请日：1997-10-10
申请人： Benoit Nadeau-Dostie , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Jean-Francois Cote
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31855
摘要： A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.-- In operation in all of the components concurrently at the rate of the Test Clock; performing the Update and Capture Operations in the first group of components at the rate of the Test Clock; and performing the Update and Capture Operations in the second group of components at the rate of the system Clock. The method employs a novel integrated circuit, test controller and boundary scan cells.
摘要翻译：一种测试具有可在高速系统时钟操作的部件的电路板的高速互连性的方法，采用IEEE 1149.1标准测试方法，其中测试数据在Shift-In期间以测试时钟的速率被移入和移出部件， Shift-Out操作，并且在Shift-In和Shift-Out操作之间具有Update操作和Capture操作，这些组件包括能够以仅测试时钟的速率执行Update和Capture操作的第一组组件，以及能够以系统时钟的速率执行更新和捕获操作的第二组组件，所述方法包括以所述测试时钟的速率同时在所有组件中执行所述移位操作的步骤; 以测试时钟的速率在第一组组件中执行更新和捕获操作; 并以系统时钟的速率在第二组组件中执行更新和捕获操作。该方法采用新颖的集成电路，测试控制器和边界扫描单元。

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