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    • 1. 发明申请
    • Masking circuit and method of masking corrupted bits
    • 掩蔽电路和掩蔽损坏位的方法
    • US20050240848A1
    • 2005-10-27
    • US11109844
    • 2005-04-20
    • Jean-Francois CotePaul PriceBenoit Nadeau-Dostie
    • Jean-Francois CotePaul PriceBenoit Nadeau-Dostie
    • G01R31/28G01R31/3185
    • G01R31/318572
    • A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.
    • 一种屏蔽电路,用于在集成电路的扫描测试期间有选择地屏蔽扫描链输入和/或输出,包括屏蔽寄存器,其具有用于每个扫描链的至少两个屏蔽寄存器元件,以提供多个屏蔽模式; 以及用于每个扫描链的输入和输出掩模控制电路,每个掩模控制电路连接在测试图案源和签名寄存器之间,并且连接在相关联的扫描链的串行输入和串行输出之间,并响应于存储的掩码控制数据 在用于在电路的扫描测试期间用于将多个掩模模式中的一个掩模模式中的一个配置为关联的扫描链的寄存器元件中。
    • 2. 发明授权
    • Apparatus for severing and separating cup-shaped object supports
    • 用于切断和分离杯形物体支架的装置
    • US4300423A
    • 1981-11-17
    • US91196
    • 1979-11-07
    • Paul Price
    • Paul Price
    • B01L99/00B26D1/547B26D3/00B01L11/00
    • B01L99/00B26D1/547Y10T83/2216Y10T83/222Y10T83/6544Y10T83/6614Y10T83/7587
    • For the purposes of severing and separating a plurality of cup-shaped object supports (2) of plastic material, which are interconnectedly arranged on a support plate (1), use is made of a method wherein the support plate (1) is first put into a gripping device (4) and secured therein. Subsequently a severing device (5) which is displaceable in the plane of the support plate (1) is set in motion to sever the cup-shaped object supports by means of a saw blade (14). The object supports (2) fall into the respectively associated glass reagent vessels (20) by way of distributor passages (18) which lead downwardly in a truncated pyramid configuration, which reagent vessels can be pushed into position below the distributor block (17) in a container carrier (19). The method according to the invention replaces the conventional operations of severing and separating the object supports (2) by a shears.
    • 为了切断和分离互连地布置在支撑板(1)上的多个塑料材料的杯形物体支撑件(2)的目的,使用其中首先放置支撑板(1)的方法 进入夹紧装置(4)并固定在其中。 随后,在支撑板(1)的平面中可移位的切断装置(5)被运动以通过锯片(14)切断杯形物体支撑件。 物体支撑件(2)通过分配器通道(18)落入分别关联的玻璃试剂容器(20)中,分配器通道(18)以截锥形结构向下引导,该试剂容器可以被推入分配器块(17)下方的位置 容器托架(19)。 根据本发明的方法取代了用剪切机切断和分离物体支撑件(2)的常规操作。
    • 8. 发明授权
    • Method and program product for completing a circuit design having embedded test structures
    • 用于完成具有嵌入式测试结构的电路设计的方法和程序产品
    • US06725435B2
    • 2004-04-20
    • US10323815
    • 2002-12-20
    • Jean-François CôtéPaul Price
    • Jean-François CôtéPaul Price
    • G06F1750
    • G06F17/5022
    • A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.
    • 用于验证电路设计中嵌入式测试结构的签名方法从电路描述中提取所有嵌入式测试结构的描述,以创建测试连接映射文件,并验证测试结构与电路引脚或网络的连接 ,创建验证配置文件以供使用,在对包含逻辑测试结构的电路执行电路的签发验证时,验证每个逻辑测试结构符合逻辑测试设计规则并创建逻辑测试向量和参考签名,执行 电路的正式验证和静态时序分析,使用验证配置文件和测试连接图文件为每个测试结构生成一个注销仿真测试台,执行测试台以模拟电路中的所有测试结构; 并创建制造测试模式。
    • 10. 发明授权
    • YKL-40 monoclonal authority
    • YKL-40单克隆抗体
    • US08053563B2
    • 2011-11-08
    • US11817244
    • 2006-02-16
    • Richard BonnichsenPaul Price
    • Richard BonnichsenPaul Price
    • C07K16/00
    • C07K16/30A61K2039/505C07K2317/34C07K2317/73
    • The present invention relates to monoclonal anti-human YKL-antibodies which are capable to modulate biological processes in which YKL-40 plays a prominent role, e.g. inhibit the growth and/or inducing apoptosis of cells, in particular cancer cells. The invention also relates to pharmaceutical compositions comprising said antibodies and uses said antibodies and/or pharmaceutical compositions for treatment of a disease wherein inhibition of cell growth, cell differentiation, remodelling of extracellular matrix, metastasis and/or induction of cell death due to apoptosis is a prerequisite for successful curing. An antibody of the invention is capable of inhibiting biological function of YKL-40 in the above mentioned processes by binding to a specific epitope on YKL-40.
    • 本发明涉及能够调节其中YKL-40起突出作用的生物学过程的单克隆抗人YKL-抗体。 抑制细胞,特别是癌细胞的生长和/或诱导细胞凋亡。 本发明还涉及包含所述抗体的药物组合物,并且使用所述抗体和/或药物组合物来治疗疾病,其中抑制细胞生长,细胞分裂,细胞外基质的重塑,转移和/或由细胞凋亡引起的细胞死亡的诱导是 成功治愈的先决条件。 本发明的抗体能够通过与YKL-40上的特异性表位结合而在上述方法中抑制YKL-40的生物学功能。