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1. 发明授权

US06510534B1 Method and apparatus for testing high performance circuits 有权
标题翻译：用于测试高性能电路的方法和装置
公开(公告)号：US06510534B1
公开(公告)日：2003-01-21
申请号：US09607128
申请日：2000-06-29
申请人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek , Jean-Francois Cote
发明人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek , Jean-Francois Cote
IPC分类号： G01R3128
CPC分类号： G11C29/56012 , G01R31/318552 , G01R31/318563 , G11C29/56 , G11C2029/3202
摘要： A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out. A test controller is clocked a test clock and includes a clock generation module for generating shift and capture clocks. The test clock can be an independent and asynchronous clock or derived from the system clock. The test can also be performed by using only the test clock in the case only the test clock is available or for diagnostic and debug purposes.
摘要翻译：通过在移位序列之后的捕获序列期间能够进行至少两个时钟脉冲来执行用于速度测试高性能数字系统和具有组合逻辑和存储元件可能是可扫描和不可扫描的电路的方法。该方法提供了在执行速度测试之前在测试开始时经由可扫描存储器元件的任何非可扫描存储器元件的初始化。在初始化期间，控制逻辑产生一个信号，以禁止生成用于捕获的系统时钟脉冲。相反，仅产生从测试时钟或系统时钟得到的一个时钟周期来初始化不可扫描元件。所需的移位序列的数量取决于两个可扫描存储器元件之间必须经过的不可扫描元件的最大数量。在相同的初始化期间，输出响应分析器被禁用，因为未知数据值将出现在数据流中。一个测试控制器是一个测试时钟，它包括一个产生移位和捕捉时钟的时钟生成模块。测试时钟可以是独立的和异步的时钟，也可以从系统时钟导出。只有在测试时钟可用或用于诊断和调试目的的情况下，也可以仅使用测试时钟进行测试。

2. 发明授权

US06615392B1 Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby 有权
标题翻译：分层设计和测试方法和系统，程序产品体现了由此产生的方法和集成电路
公开(公告)号：US06615392B1
公开(公告)日：2003-09-02
申请号：US09626877
申请日：2000-07-27
申请人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
发明人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
IPC分类号： G06F945
CPC分类号： G01R31/318591 , G01R31/318586
摘要： A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
摘要翻译：一种在具有至少一个模块的集成电路的分级设计中使用的方法，每个模块具有功能存储元件和组合逻辑，该方法包括读取电路的描述; 用扫描模式和捕获模式可配置的可扫描存储器元件的描述代替模块的每个功能存储元件的描述; 通过将所选择的可扫描存储器元件的描述转换为在内部测试模式，外部测试模式和正常操作模式中可配置的外围可扫描存储器元件的描述，将每个模块分成内部分区和外围分区; 修改电路描述中的模块的描述，以便将存储器元件布置成扫描链，其中当配置在内部测试模式中时，由模块测试控制器控制每个模块的外围和内部可扫描存储元件; 并且当在外部测试模式下配置时，每个模块的外围可扫描存储器元件由顶级测试控制器控制; 并验证电路的内部测试模式和外部测试模式的正确操作。

3. 发明授权

US6145105A Method and apparatus for scan testing digital circuits 有权
标题翻译：扫描测试数字电路的方法和装置
公开(公告)号：US6145105A
公开(公告)日：2000-11-07
申请号：US192839
申请日：1998-11-16
申请人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote , Dwayne Burek
发明人： Benoit Nadeau-Dostie , Jean-Fran.cedilla.ois Cote , Dwayne Burek
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31858 , G01R31/318536
摘要： A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.
摘要翻译：一种用于测试可扫描存储器和组合网络的方法和数字系统。可扫描存储器可配置成几个扫描链。每个链可以具有由相应的时钟使能信号确定的不同的有效时钟速率。该方法和数字系统允许对使用单个操作时钟速率的数字电路和几个功能时钟使能信号进行扫描测试来实现较慢的锁定工作速率。数字系统包括具有扫描使能和时钟使能输入的存储器元件。

4. 发明授权

US06457161B1 Method and program product for modeling circuits with latch based design 有权
标题翻译：用于基于闩锁设计的电路建模方法和程序产品
公开(公告)号：US06457161B1
公开(公告)日：2002-09-24
申请号：US09817298
申请日：2001-03-27
申请人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
发明人： Benoit Nadeau-Dostie , Fadi Maamari , Dwayne Burek
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.
摘要翻译：一种用于对具有组合逻辑和锁存器的逻辑电路进行建模的方法和计算机程序产品，其中锁存器由第一时钟相位，第二时钟相位或从第二时钟相位导出的脉冲之一计时，锁存器的子集可扫描的，包括对于逻辑电路中的每个锁存器，将锁存器与第一和第二时钟相位之一相关联; 并且当锁存器与第一时钟相关联时，将锁存器建模为连接在锁存器的数据输入和输出之间的缓冲器; 并且当锁存器与第二时钟相关联时，将锁存器建模为具有与锁存器相同的数据输入，数据输出和时钟输入的边沿触发触发器。

5. 发明授权

US06862717B2 Method and program product for designing hierarchical circuit for quiescent current testing 有权
标题翻译：用于设计静态电流测试分层电路的方法和程序产品
公开(公告)号：US06862717B2
公开(公告)日：2005-03-01
申请号：US10015751
申请日：2001-12-17
申请人： Benoit Nadeau-Dostie , Dwayne Burek
发明人： Benoit Nadeau-Dostie , Dwayne Burek
IPC分类号： G01R31/30 , G01R31/3185 , G06F17/50
CPC分类号： G01R31/318555 , G01R31/3004 , G01R31/318577 , G01R31/31858
摘要： A method of designing a circuit having at least one hierarchical block which requires block specific test patterns to facilitate quiescent current testing of the circuit, comprises, for each block, configuring the block and any embedded blocks located one level down in design hierarchy in quiescent current test mode in which input and output peripheral memory elements are configured in internal test mode and in external test mode, respectively; generating quiescent current test patterns which do not result in elevated quiescent current levels and which include a bit for all memory elements in the block and for any peripheral memory elements in any embedded blocks located one level down in design hierarchy; and, if the block contains embedded blocks, synchronizing the test pattern with a corresponding test pattern generated for embedded blocks so that test patterns loaded in scan chains in the block are consistent with test patterns loaded in scan chains in said embedded blocks.
摘要翻译：一种设计具有至少一个分层块的电路的方法，其需要块特定的测试模式以便于电路的静态电流测试，对于每个块，包括在静态电流的设计层级中配置块和任意一个位于一级的嵌入块输入和输出外围存储器元件分别在内部测试模式和外部测试模式下配置的测试模式; 产生静态电流测试模式，这些静态电流测试模式不会导致静态电流电平的提高，并且包括块中所有存储器元件的位以及位于设计层级中一级下降的任何嵌入式模块中的任何外围存储器元件的位; 并且如果块包含嵌入块，则将测试模式与针对嵌入块生成的对应测试模式同步，使得加载到块中的扫描链中的测试模式与在所述嵌入块中的扫描链中加载的测试模式一致。

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