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1. 发明授权

US07191374B2 Method of and program product for performing gate-level diagnosis of failing vectors 有权
标题翻译：用于执行故障向量的门级诊断的方法和程序产品
公开(公告)号：US07191374B2
公开(公告)日：2007-03-13
申请号：US10435094
申请日：2003-05-12
申请人： Fadi Maamari , Sonny Ngai San Shum , Benoit Nadeau-Dostie
发明人： Fadi Maamari , Sonny Ngai San Shum , Benoit Nadeau-Dostie
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/2891 , G01R31/3177
摘要： A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.
摘要翻译：一种具有故障测试向量的集成电路的故障诊断方法，具有使用通过仿真一组测试向量获得的故障候选故障效应的具有观察到的故障效应的故障诊断方法，包括确定每个故障候选的故障候选诊断测量，所述故障候选诊断测量具有故障候选匹配度量，观察到的故障效应不匹配度量和故障候选激励度量，降低诊断测量顺序对故障候选进行排序; 并且将具有最高诊断度量的故障候选者识别为观察到的故障效应的最可能的原因。

2. 发明授权

US06615392B1 Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby 有权
标题翻译：分层设计和测试方法和系统，程序产品体现了由此产生的方法和集成电路
公开(公告)号：US06615392B1
公开(公告)日：2003-09-02
申请号：US09626877
申请日：2000-07-27
申请人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
发明人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
IPC分类号： G06F945
CPC分类号： G01R31/318591 , G01R31/318586
摘要： A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
摘要翻译：一种在具有至少一个模块的集成电路的分级设计中使用的方法，每个模块具有功能存储元件和组合逻辑，该方法包括读取电路的描述; 用扫描模式和捕获模式可配置的可扫描存储器元件的描述代替模块的每个功能存储元件的描述; 通过将所选择的可扫描存储器元件的描述转换为在内部测试模式，外部测试模式和正常操作模式中可配置的外围可扫描存储器元件的描述，将每个模块分成内部分区和外围分区; 修改电路描述中的模块的描述，以便将存储器元件布置成扫描链，其中当配置在内部测试模式中时，由模块测试控制器控制每个模块的外围和内部可扫描存储元件; 并且当在外部测试模式下配置时，每个模块的外围可扫描存储器元件由顶级测试控制器控制; 并验证电路的内部测试模式和外部测试模式的正确操作。

3. 发明授权

US06883134B2 Method and program product for detecting bus conflict and floating bus conditions in circuit designs 有权
标题翻译：用于检测电路设计中总线冲突和浮动总线条件的方法和程序产品
公开(公告)号：US06883134B2
公开(公告)日：2005-04-19
申请号：US09817299
申请日：2001-03-27
申请人： Fadi Maamari , Sonny Ngai San Shum
发明人： Fadi Maamari , Sonny Ngai San Shum
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F17/5022
摘要： A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a min-cut, of the logic controlling the bus, performing an exhaustive analysis on a min-cut set of logic, and performing a full exhaustive analysis of the bus when the exhaustive analysis on the min-cut set of logic is inconclusive. In a preferred embodiment, prior to performing the min-cut set analysis, implication based conflict-free and float-free analyses are performed on the bus.
摘要翻译：一种用于验证设计中三态总线正常操作的逻辑设计的方法和程序产品，包括对于电路设计中的每个总线，确定控制总线的逻辑的最小切割集，最小切割，对最小限度的逻辑集进行详尽的分析，并对最小限度的逻辑集合进行彻底的分析是不确定的，对总线进行全面详尽的分析。在优选实施例中，在执行最小切割集分析之前，在总线上执行基于冲突和无浮动分析的暗示。

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