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1. 发明授权

US08501596B2 Method for fabricating a micro-electronic device equipped with semi-conductor zones on an insulator with a horizontal GE concentration gradient 有权
标题翻译：用于制造具有水平GE浓度梯度的绝缘体上具有半导体区的微电子器件的方法
公开(公告)号：US08501596B2
公开(公告)日：2013-08-06
申请号：US12560867
申请日：2009-09-16
申请人： Benjamin Vincent , Vincent Destefanis
发明人： Benjamin Vincent , Vincent Destefanis
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02636 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/1054 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A manufacturing method of a microelectronic device including at least one semi-conductor zone which rests on a support and which exhibits a germanium concentration gradient in a direction parallel to the principal pane of the support.
摘要翻译：一种微电子器件的制造方法，其包括至少一个半导体区，该半导体区位于支撑体上并且在平行于载体的主窗格的方向上显示锗浓度梯度。

2. 发明授权

US08530339B2 Method for direct deposition of a germanium layer 有权
标题翻译：直接沉积锗层的方法
公开(公告)号：US08530339B2
公开(公告)日：2013-09-10
申请号：US13347834
申请日：2012-01-11
申请人： Benjamin Vincent , Matty Caymax , Roger Loo , Johan Dekoster
发明人： Benjamin Vincent , Matty Caymax , Roger Loo , Johan Dekoster
IPC分类号： H01L29/16
CPC分类号： C23C16/22 , C23C16/28 , H01L21/02381 , H01L21/02488 , H01L21/02491 , H01L21/02532 , H01L21/02573 , H01L21/0262
摘要： The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH4), is applied. In an example embodiment, the deposition is done under application of a deposition temperature between 275° C. and 500° C., with the partial pressure of the precursor gas within the mixture being at least 20 mTorr for temperatures between 275° C. and 285° C., and at least 10 mTorr for temperatures between 285° and 500° C.
摘要翻译：本公开涉及通过化学气相沉积在基底上沉积锗的连续层的方法。根据本公开，应用非反应性载气和高级锗前体气体，即高于锗烷（GeH 4）的混合物。在一个示例性实施例中，沉积在275℃至500℃之间的沉积温度下进行，混合物中前体气体的分压至少为20mTorr，温度为275℃至 285°C，至少10 mTorr，温度在285°和500°C之间。

3. 发明授权

US08569801B2 Three-dimensional CMOS circuit on two offset substrates and method for making same 有权
标题翻译：两个偏移基板上的三维CMOS电路及其制造方法
公开(公告)号：US08569801B2
公开(公告)日：2013-10-29
申请号：US13059483
申请日：2009-08-10
申请人： Benjamin Vincent
发明人： Benjamin Vincent
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.
摘要翻译：分别形成在第一和第二晶体基板上的具有至少第一N导电场效应晶体管和第二P导电场效应晶体管的三维CMOS电路。第一场效应晶体管在第一衬底中具有第一次级晶体取向。第二场效应晶体管在第二衬底中具有第二次晶体取向。第一和第二晶体管的取向与其中一个衬底中形成的角度形成与第一和第二次晶界方向不同的角度。第一和第二基板垂直组装。

4. 发明授权

US08247313B2 Method for preparing a germanium layer from a silicon-germanium-on-isolator substrate 有权
标题翻译：从硅 - 锗隔离器衬底制备锗层的方法
公开(公告)号：US08247313B2
公开(公告)日：2012-08-21
申请号：US12525756
申请日：2008-02-07
申请人： Benjamin Vincent , Jean-Francois Damlencourt , Yves Morand
发明人： Benjamin Vincent , Jean-Francois Damlencourt , Yves Morand
IPC分类号： H01L21/20 , H01L21/336
CPC分类号： H01L21/7624 , H01L21/28518
摘要： A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors.
摘要翻译：一种从SGOI衬底制造绝缘体上锗层的方法，包括：a）在衬底上沉积能够选择性地形成硅化物的金属元素M的层，该层与硅 - 锗合金层接触 ; 以及b）合金层与金属元素M层之间的反应，通过该反应得到一叠M硅化物 - 锗 - 绝缘体层。这种方法可以例如用于生产诸如MOSFET晶体管的电子器件。

5. 发明授权

US08709918B2 Method for selective deposition of a semiconductor material 有权
标题翻译：选择性沉积半导体材料的方法
公开(公告)号：US08709918B2
公开(公告)日：2014-04-29
申请号：US13351344
申请日：2012-01-17
申请人： Benjamin Vincent , Roger Loo , Matty Caymax
发明人： Benjamin Vincent , Roger Loo , Matty Caymax
IPC分类号： H01L21/20
CPC分类号： H01L21/0237 , H01L21/02532 , H01L21/02535 , H01L21/02573 , H01L21/0262 , H01L21/02636
摘要： A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.
摘要翻译：公开了一种在半导体处理中选择性沉积半导体材料的方法。在一些实施例中，该方法包括提供包括第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，第二区域包括暴露的绝缘体材料。该方法还包括通过提供第二半导体材料的前体，与氯化合物不反应的载气和四氯化锡（SnCl 4），选择性地在第一区域的第一半导体材料上提供第二半导体材料的膜，。四氯化锡抑制第二半导体材料沉积在第二区域的绝缘体材料上。

6. 发明申请

US20090170295A1 MANUFACTURING METHOD FOR A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE COMPRISING A LOCALISED Ge ENRICHED STEP 有权
标题翻译：一种半导体制造方法，该绝缘体基板包含一个本地化的加固步骤
公开(公告)号：US20090170295A1
公开(公告)日：2009-07-02
申请号：US12340839
申请日：2008-12-22
申请人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
发明人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
IPC分类号： H01L21/20
CPC分类号： H01L21/32105 , H01L21/7624
摘要： The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.The method comprises the following steps: formation of a silicon oxide layer on the layer of Si1-xGex, formation of a silicon oxide layer on the layer of Si1-xGex, etching of the stack formed by the superficial layer of silicon, the layer of Si1-xGex and the silicon oxide layer, wherein the etching is carried out either up to the buried insulating layer to obtain an etched structure with at least one island of said stack, or up to the superficial layer of silicon to obtain an etched structure with at least one zone of silicon and at least one island of said stack, formation of a mask to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island, condensation of the germanium of the layer of Si1-xGex on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the buried insulating layer, with a silicon oxide layer on top of it.
摘要翻译：本发明涉及一种绝缘体上半导体衬底的制造方法，该SOI衬底包括在绝缘层上称为掩埋绝缘层的硅表面层，其中Si1-xGex层形成在表面层上硅。该方法包括以下步骤：在Si1-xGex层上形成氧化硅层，在Si1-xGex层上形成氧化硅层，蚀刻由硅表面层形成的叠层 Si1-xGex和氧化硅层，其中蚀刻直到埋入绝缘层进行，以获得具有至少一个所述堆叠的岛的蚀刻结构，或直到硅的表面层，以获得具有硅的至少一个区域和所述堆叠的至少一个岛，形成掩模以防止在蚀刻结构上的氧化，其中所述保护掩模仅使所述岛的氧化硅层可见，所述层的锗的冷凝的Si1-xGex，以在掩埋绝缘层上形成富含锗或甚至一层锗的层，其上面具有氧化硅层。

7. 发明申请

US20110140178A1 THREE-DIMENSIONAL CMOS CIRCUIT ON TWO OFFSET SUBSTRATES AND METHOD FOR MAKING SAME 有权
标题翻译：两个偏移基板上的三维CMOS电路及其制造方法
公开(公告)号：US20110140178A1
公开(公告)日：2011-06-16
申请号：US13059483
申请日：2009-08-10
申请人： Benjamin Vincent
发明人： Benjamin Vincent
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.
摘要翻译：分别形成在第一和第二晶体基板上的具有至少第一N导电场效应晶体管和第二P导电场效应晶体管的三维CMOS电路。第一场效应晶体管在第一衬底中具有第一次级晶体取向。第二场效应晶体管在第二衬底中具有第二次晶体取向。第一和第二晶体管的取向与其中一个衬底中形成的角度形成与第一和第二次晶界方向不同的角度。第一和第二基板垂直组装。

8. 发明申请

US20100044836A1 PROCESS FOR PRODUCING LOCALISED Ge0I STRUCTURES, OBTAINED BY GERMANIUM CONDENSATION 有权
标题翻译：用于生产本地化的Ge0I结构的方法，由德国凝固获得
公开(公告)号：US20100044836A1
公开(公告)日：2010-02-25
申请号：US12539713
申请日：2009-08-12
申请人： Jean-François Damlencourt , Benjamin Vincent
发明人： Jean-François Damlencourt , Benjamin Vincent
IPC分类号： H01L29/161 , H01L21/762
CPC分类号： H01L21/31658 , H01L21/02203 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/7624 , H01L29/1054 , H01L29/78
摘要： The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
摘要翻译：本发明涉及通过由氧化硅层支撑的SiGe层的锗缩合制备至少一种GeOI结构的方法。氧化硅层掺杂锗，二氧化硅层中锗的浓度使得低于氧化温度的氧化硅层的流动温度降低，允许SiGe层的锗冷凝。

9. 发明授权

US09040391B2 Process for producing localised GeOI structures, obtained by germanium condensation 有权
标题翻译：通过锗缩合获得的局部GeOI结构的制备方法
公开(公告)号：US09040391B2
公开(公告)日：2015-05-26
申请号：US12539713
申请日：2009-08-12
申请人： Jean-François Damlencourt , Benjamin Vincent
发明人： Jean-François Damlencourt , Benjamin Vincent
IPC分类号： H01L21/20 , H01L21/316 , H01L21/02 , H01L21/28 , H01L21/762 , H01L29/10 , H01L29/78
CPC分类号： H01L21/31658 , H01L21/02203 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/7624 , H01L29/1054 , H01L29/78
摘要： The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
摘要翻译：本发明涉及通过由氧化硅层支撑的SiGe层的锗缩合制备至少一种GeOI结构的方法。氧化硅层掺杂锗，二氧化硅层中锗的浓度使得低于氧化温度的氧化硅层的流动温度降低，允许SiGe层的锗冷凝。

10. 发明申请

US20140020619A1 Method for Growing a Monocrystalline Tin-Containing Semiconductor Material 审中-公开
标题翻译：生产含单晶锡的半导体材料的方法
公开(公告)号：US20140020619A1
公开(公告)日：2014-01-23
申请号：US14008560
申请日：2012-03-29
申请人： Benjamin Vincent , Federica Gencarelli , Roger Loo , Matty Caymax
发明人： Benjamin Vincent , Federica Gencarelli , Roger Loo , Matty Caymax
IPC分类号： H01L21/02
CPC分类号： H01L21/02535 , B33Y80/00 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L31/02 , H01L31/048 , H01L31/055 , Y02E10/52
摘要： Disclosed are methods for growing Sn-containing semiconductor materials. In some embodiments, an example method includes providing a substrate in a chemical vapor deposition (CVD) reactor, and providing a semiconductor material precursor, a Sn precursor, and a carrier gas in the CVD reactor. The method further includes epitaxially growing a Sn-containing semiconductor material on the substrate, where the Sn precursor comprises tin tetrachloride (SnCl4). The semiconductor material precursor may be, for example, digermane, trigermane, higher-order germanium precursors, or a combination thereof. Alternatively, the semiconductor material precursor may be a silicon precursor.
摘要翻译：公开了用于生长含Sn半导体材料的方法。在一些实施例中，示例性方法包括在化学气相沉积（CVD）反应器中提供衬底，以及在CVD反应器中提供半导体材料前体，Sn前体和载气。该方法还包括在衬底上外延生长含Sn半导体材料，其中Sn前体包括四氯化锡（SnCl 4）。半导体材料前体可以是例如二摩尔，三面体，高级锗前体，或其组合。或者，半导体材料前体可以是硅前体。

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