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1. 发明授权

US07759175B2 Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权
标题翻译：混合基板的制造方法和用于制造电路的基板的使用
公开(公告)号：US07759175B2
公开(公告)日：2010-07-20
申请号：US12071886
申请日：2008-02-27
申请人： Laurent Clavelier , Cyrille Le Royer , Jean-François Damlencourt
发明人： Laurent Clavelier , Cyrille Le Royer , Jean-François Damlencourt
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译：包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区。在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。

2. 发明申请

US20100044836A1 PROCESS FOR PRODUCING LOCALISED Ge0I STRUCTURES, OBTAINED BY GERMANIUM CONDENSATION 有权
标题翻译：用于生产本地化的Ge0I结构的方法，由德国凝固获得
公开(公告)号：US20100044836A1
公开(公告)日：2010-02-25
申请号：US12539713
申请日：2009-08-12
申请人： Jean-François Damlencourt , Benjamin Vincent
发明人： Jean-François Damlencourt , Benjamin Vincent
IPC分类号： H01L29/161 , H01L21/762
CPC分类号： H01L21/31658 , H01L21/02203 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/7624 , H01L29/1054 , H01L29/78
摘要： The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
摘要翻译：本发明涉及通过由氧化硅层支撑的SiGe层的锗缩合制备至少一种GeOI结构的方法。氧化硅层掺杂锗，二氧化硅层中锗的浓度使得低于氧化温度的氧化硅层的流动温度降低，允许SiGe层的锗冷凝。

3. 发明授权

US09040391B2 Process for producing localised GeOI structures, obtained by germanium condensation 有权
标题翻译：通过锗缩合获得的局部GeOI结构的制备方法
公开(公告)号：US09040391B2
公开(公告)日：2015-05-26
申请号：US12539713
申请日：2009-08-12
申请人： Jean-François Damlencourt , Benjamin Vincent
发明人： Jean-François Damlencourt , Benjamin Vincent
IPC分类号： H01L21/20 , H01L21/316 , H01L21/02 , H01L21/28 , H01L21/762 , H01L29/10 , H01L29/78
CPC分类号： H01L21/31658 , H01L21/02203 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/7624 , H01L29/1054 , H01L29/78
摘要： The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
摘要翻译：本发明涉及通过由氧化硅层支撑的SiGe层的锗缩合制备至少一种GeOI结构的方法。氧化硅层掺杂锗，二氧化硅层中锗的浓度使得低于氧化温度的氧化硅层的流动温度降低，允许SiGe层的锗冷凝。

4. 发明授权

US07494831B2 Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material 有权
标题翻译：用于制造由封装在另一种半导体材料中的一种半导体材料制成的岛叠的方法
公开(公告)号：US07494831B2
公开(公告)日：2009-02-24
申请号：US11202316
申请日：2005-08-12
申请人： Jean-François Damlencourt , Benoît Vandelle
发明人： Jean-François Damlencourt , Benoît Vandelle
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/0259 , H01L21/0262 , H01L29/127
摘要： The invention relates to the production of a stacked structure of planes of islands of a first semiconducting material encapsulated in a second semiconducting material on a substrate, comprising alternate deposition of planes of islands of a first semiconducting material and encapsulation layers of a second semiconducting material, the planes of islands of the first semiconducting material being made at an optimum growth temperature and at an optimum precursor gas partial pressure to result in a stacked structure for which the optical properties enable production of optoelectronic components to optically interconnect integrated circuits. The stacked structure is made on a plane of islands of a third semiconducting material called the sacrificial plane encapsulated in a fourth semiconducting material, the islands of the sacrificial plane being made under growth conditions that can result in high densities of small islands, in other words at a temperature below the optimum growth temperature and/or at a precursor gas partial pressure greater than the optimum partial pressure.
摘要翻译：本发明涉及在衬底上封装在第二半导体材料中的第一半导体材料的岛的平面的叠层结构的制造，包括第一半导体材料的岛的平面和第二半导体材料的封装层的交替沉积，第一半导体材料的岛的平面在最佳生长温度和最佳前体气体分压下制成，以产生光学特性使得能够制造光电组件以光学互连集成电路的堆叠结构。叠层结构在被称为牺牲平面的第三半导体材料的岛的平面上形成，该第三半导体材料被封装在第四半导体材料中，牺牲平面的岛被制成在可导致高密度的小岛的生长条件下，换句话说在低于最佳生长温度的温度和/或大于最佳分压的前体气体分压下。

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